Patents by Inventor Won Bae Bang
Won Bae Bang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200411397Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: ApplicationFiled: September 11, 2020Publication date: December 31, 2020Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Publication number: 20200395272Abstract: A semiconductor device comprises a substrate having a substrate top side, a substrate lateral side, and a substrate bottom side, an electronic device on the substrate top side, and an encapsulant on the substrate top side and contacting a lateral surface of the electronic device. The substrate comprises a conductive structure and a dielectric structure that extends comprising a protrusion in contact with the encapsulant. The conductive structure comprises a lead comprising a lead flank, the lead flank comprising a cavity and a conductive coating on a surface of the lead in the cavity. The conductive structure comprises a pad exposed at the substrate top side, embedded in the dielectric structure, and adjacent to the protrusion, to electrically couple with the electronic device via a first internal interconnect. Other examples and related methods are also disclosed herein.Type: ApplicationFiled: June 11, 2019Publication date: December 17, 2020Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Won Bae Bang, Kwang Seok Oh, George Scott
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Publication number: 20200381395Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.Type: ApplicationFiled: June 3, 2019Publication date: December 3, 2020Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee
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Publication number: 20200273789Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process.Type: ApplicationFiled: November 4, 2019Publication date: August 27, 2020Inventors: Seung Woo Lee, Byong Jin Kim, Won Bae Bang, Sang Goo Kang
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Publication number: 20200258803Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.Type: ApplicationFiled: April 29, 2020Publication date: August 13, 2020Applicant: Amkor Technology Singapore Holding Pte. LtdInventors: Won Bae BANG, Byong Jin KIM, Gi Jeong KIM, Jae Doo KWON, Hyung Il JEON
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Patent number: 10685897Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.Type: GrantFiled: July 11, 2018Date of Patent: June 16, 2020Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Jae Doo Kwon, Hyung Il Jeon
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Patent number: 10468343Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process.Type: GrantFiled: January 18, 2018Date of Patent: November 5, 2019Assignee: Amkor Technology, Inc.Inventors: Seung Woo Lee, Byong Jin Kim, Won Bae Bang, Sang Goo Kang
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Publication number: 20190326206Abstract: A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Inventors: Won Bae Bang, Kwang Seok Oh
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Patent number: 10340213Abstract: A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.Type: GrantFiled: March 14, 2016Date of Patent: July 2, 2019Assignee: AMKOR TECHNOLOGY, INC.Inventors: Won Bae Bang, Kwang Seok Oh
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Patent number: 10224218Abstract: In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die.Type: GrantFiled: June 3, 2016Date of Patent: March 5, 2019Assignee: Amkor Technology Inc.Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Ji Young Chung
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Patent number: 10177117Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.Type: GrantFiled: April 19, 2016Date of Patent: January 8, 2019Assignee: Amkor Technology Inc.Inventors: Won Bae Bang, Ju Hoon Yoon, Ji Young Chung, Byong Jin Kim, Gi Jeong Kim, Choon Heung Lee
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Publication number: 20180323129Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.Type: ApplicationFiled: July 11, 2018Publication date: November 8, 2018Applicant: Amkor Technology Inc.Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Jae Doo Kwon, Hyung Il Jeon
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Patent number: 10049954Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.Type: GrantFiled: June 3, 2016Date of Patent: August 14, 2018Assignee: Amkor Technology, Inc.Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Jae Doo Kwon, Hyung Il Jeon
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Publication number: 20180158767Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.Type: ApplicationFiled: February 3, 2018Publication date: June 7, 2018Applicant: Amkor Technology, Inc.Inventors: Won Bae BANG, Byong Jin KIM, Gi Jeong KIM, Ji Young CHUNG
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Publication number: 20180145019Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process.Type: ApplicationFiled: January 18, 2018Publication date: May 24, 2018Inventors: Seung Woo Lee, Byong Jin Kim, Won Bae Bang, Sang Goo Kang
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Patent number: 9978695Abstract: A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.Type: GrantFiled: March 13, 2017Date of Patent: May 22, 2018Assignee: Amkor Technology, Inc.Inventors: Jae Min Bae, Byong Jin Kim, Won Bae Bang
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Patent number: 9922919Abstract: In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.Type: GrantFiled: December 30, 2015Date of Patent: March 20, 2018Assignee: AMKOR TECHNOLOGY, INC.Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Ji Young Chung
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Patent number: 9881864Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process.Type: GrantFiled: April 3, 2017Date of Patent: January 30, 2018Assignee: AMKOR TECHNOLOGY, INC.Inventors: Seung Woo Lee, Byong Jin Kim, Won Bae Bang, Sang Goo Kang
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Publication number: 20170263543Abstract: A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.Type: ApplicationFiled: March 14, 2016Publication date: September 14, 2017Inventors: Won Bae Bang, Kwang Seok Oh
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Publication number: 20170207162Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process.Type: ApplicationFiled: April 3, 2017Publication date: July 20, 2017Inventors: Seung Woo Lee, Byong Jin Kim, Won Bae Bang, Sang Goo Kang