Patents by Inventor Won-Geun CHOI
Won-Geun CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240121956Abstract: A semiconductor device may include: first insulating pillars arranged in a first direction; second insulating pillars arranged alternately with the first insulating pillars and having a first width in the first direction and a second width in a second direction intersecting the first direction, the first width being greater than the second width; first memory cells located between the second insulating pillars and stacked along a first sidewall of each of the first insulating pillars; and second memory cells located between the second insulating pillars and stacked along a second sidewall of each of the first insulating pillars.Type: ApplicationFiled: March 31, 2023Publication date: April 11, 2024Inventors: Rho Gyu KWAK, In Su PARK, Jung Shik JANG, Seok Min CHOI, Won Geun CHOI
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Publication number: 20240081072Abstract: A memory device and a method of manufacturing the same. The memory device may include a stacked structure including a drain selection line, word lines, and a source selection line that are sequentially stacked, a main plug extending in a vertical direction of the stacked structure, and including a sub-source layer hole in a central portion of an upper area of the main plug, a separation pattern configured to separate the main plug in a vertical direction, and a source line stacked on the stacked structure, and configured to fill the sub-source layer hole.Type: ApplicationFiled: February 28, 2023Publication date: March 7, 2024Inventors: Won Geun CHOI, Jung Shik JANG
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Publication number: 20240081071Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first stack structure including a word line of a first group and select lines of a first group; a second stack structure including select lines of a second group; a first plug in the first stack structure; a second plug connected to the first plug, the second plug being disposed in the second stack structure; a first isolation pattern between the select lines of the first group; and a second isolation pattern between the select lines of the second group.Type: ApplicationFiled: February 27, 2023Publication date: March 7, 2024Applicant: SK hynix Inc.Inventors: Jung Shik JANG, Mi Seong PARK, In Su PARK, Won Geun CHOI, Jung Dal CHOI
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Patent number: 11925059Abstract: An organic light emitting diode display device includes a substrate having an emitting area and a non-emitting area. An insulating layer is on the substrate, and the insulating layer includes a plurality of convex portions, a plurality of connecting portions and at least one wall in the emitting area. A height of the at least one wall is greater than a height of the plurality of convex portions. A first electrode is on the substream, emitting layer is on the first electrode, a second electrode is on the emitting layer. The first electrode, the emitting layer and the second electrode constitute a light emitting diode.Type: GrantFiled: June 30, 2020Date of Patent: March 5, 2024Assignee: LG Display Co., Ltd.Inventors: Hyun-Soo Lim, Kang-Ju Lee, Soo-Kang Kim, Won-Hoe Koo, Min-Geun Choi
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Publication number: 20240049466Abstract: A memory device, and a method of manufacturing the same, includes a stacked structure including gate lines stacked to be spaced apart from each other. The memory device also includes a first channel structure vertical to the gate lines and including a major axis in a first direction. The memory device further includes a second channel structure configured to separate the first channel structure and including a major axis in a second direction orthogonal to the first direction. The first channel structure includes a first memory cell group and a second memory cell group separated from each other by the second channel structure. The second channel structure includes a third memory cell group and a fourth memory cell group separated from each other in the second direction.Type: ApplicationFiled: February 6, 2023Publication date: February 8, 2024Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Mi Seong PARK, In Su PARK, Jung Shik JANG, Jung Dal CHOI
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Publication number: 20240023332Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a gate stacked structure including conductive layers, each of the conductive layers extending in a first direction and a second direction and including a top surface facing a third direction, wherein the conductive layers are stacked to be spaced apart from each other in the third direction. Also, the semiconductor memory device includes a first channel structure and a second channel structure extending in the third direction to pass through the gate stacked structure and spaced apart from each other in the second direction, a first insulating layer disposed over the gate stacked structure, an etch stop layer disposed over the first insulating layer and including a trench, an insulating material in the trench, and a bit line contact passing through the insulating material.Type: ApplicationFiled: January 18, 2023Publication date: January 18, 2024Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Mi Seong PARK, Jung Shik JANG
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Publication number: 20230395495Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a stack structure including gate lines stacked to be spaced apart from each other; main plugs arranged to be spaced apart from each other; plug isolation patterns isolating the main plugs into first and second sub-plugs; and a select isolation pattern isolating at least one gate line located between the plug isolation patterns adjacent to each other.Type: ApplicationFiled: January 11, 2023Publication date: December 7, 2023Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Jeong Hwan KIM, Mi Seong PARK, Jung Shik JANG
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Publication number: 20230395424Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.Type: ApplicationFiled: August 15, 2023Publication date: December 7, 2023Applicant: SK hynix Inc.Inventors: Dong Hun LEE, Jeong Hwan KIM, Mi Seong PARK, Jung Shik JANG, Won Geun CHOI
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Publication number: 20230320094Abstract: A memory device, and a method of manufacturing the same, includes a stack structure and main plugs passing through the stack structure, the main plugs being spaced apart from each other in a first direction. The memory device also includes a separation pattern separating the main plugs in a second direction and a slit pattern separating the stack structure into first and second memory blocks, the slit pattern having an ellipse shape.Type: ApplicationFiled: September 20, 2022Publication date: October 5, 2023Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Mi Seong PARK, Jung Shik JANG
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Patent number: 11769689Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.Type: GrantFiled: June 11, 2021Date of Patent: September 26, 2023Assignee: SK hynix Inc.Inventors: Dong Hun Lee, Jeong Hwan Kim, Mi Seong Park, Jung Shik Jang, Won Geun Choi
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Publication number: 20230301092Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; at least one channel structure penetrating the gate structure, the at least one channel structure being aligned in a first direction; a first cutting structure extending in the first direction, the first cutting structure penetrating the at least one channel structure; a contact pad in contact with an upper surface of the at least one channel structure, the contact pad having a critical dimension greater than a critical dimension of the upper surface of the at least one channel structure; and a second cutting structure in contact with an upper surface of the first cutting structure and penetrating the contact pad.Type: ApplicationFiled: August 25, 2022Publication date: September 21, 2023Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Jung Shik JANG
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Publication number: 20230126213Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first stack structure over a lower structure in which a cell region and a slimming region are defined, including a plurality of first gate lines, a first interlayer insulating structure over the first stack structure, a second stack structure over the first interlayer insulating structure, and a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure and the second stack structure in the cell region.Type: ApplicationFiled: May 26, 2022Publication date: April 27, 2023Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Jang Won KIM, Jung Shik JANG
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Publication number: 20230016278Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a first channel structure and a second channel structure, extending in a first direction; a third channel structure disposed between the first channel structure and the second channel structure, the third channel structure extending in the first direction; and a plurality of conductive layers surrounding the first channel structure, the second channel structure, and the third channel structure, the plurality of conductive layers being stacked to be spaced apart from each other in the first direction. The third channel structure is spaced apart from the first channel structure and the second channel structure without interposition of the plurality of conductive layers.Type: ApplicationFiled: June 20, 2022Publication date: January 19, 2023Applicant: SK hynix Inc.Inventor: Won Geun CHOI
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Publication number: 20220399364Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.Type: ApplicationFiled: November 30, 2021Publication date: December 15, 2022Applicant: SK hynix Inc.Inventors: Jang Won KIM, Mi Seong PARK, In Su PARK, Jung Shik JANG, Won Geun CHOI
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Publication number: 20220344366Abstract: A semiconductor device includes a gate structure including conductive layers and insulating layers alternately stacked with each other, channel structures passing through the gate structure and arranged in a first direction, a cutting structure extending in the first direction and passing through the channel structures, and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.Type: ApplicationFiled: September 23, 2021Publication date: October 27, 2022Applicant: SK hynix Inc.Inventors: Mi Seong PARK, Jang Won KIM, In Su PARK, Jung Shik JANG, Won Geun CHOI, Jung Dal CHOI
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Publication number: 20220271055Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.Type: ApplicationFiled: August 11, 2021Publication date: August 25, 2022Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Jung Shik JANG, Jang Won KIM, Mi Seong PARK
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Publication number: 20220172985Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.Type: ApplicationFiled: June 11, 2021Publication date: June 2, 2022Applicant: SK hynix Inc.Inventors: Dong Hun Lee, Jeong Hwan Kim, Mi Seong Park, Jung Shik Jang, Won Geun Choi
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Patent number: 10460628Abstract: A tile map service (TMS) device and method are provided. The TMS device includes a storage configured to store map layers that have different map types, map data of an image tile form having a level of detail (LOD) structure of each of the map layers, and a tile map in which image tile maps of a plurality of map layers are merged; a communicator configured to receive map request information including two or more map types, an LOD level, and arbitrary map coordinates from a client; and a provider configured to provide a tile map corresponding to the map request information to the client.Type: GrantFiled: May 24, 2017Date of Patent: October 29, 2019Assignee: Electronics and Telecommunications Research InstituteInventors: Yoon Seop Chang, In Sung Jang, Jae Min Seol, In Hak Joo, Won Geun Choi
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Publication number: 20170345342Abstract: A tile map service (TMS) device and method are provided. The TMS device includes a storage configured to store map layers that have different map types, map data of an image tile form having a level of detail (LOD) structure of each of the map layers, and a tile map in which image tile maps of a plurality of map layers are merged; a communicator configured to receive map request information including two or more map types, an LOD level, and arbitrary map coordinates from a client; and a provider configured to provide a tile map corresponding to the map request information to the client.Type: ApplicationFiled: May 24, 2017Publication date: November 30, 2017Applicant: Electronics and Telecommunications Research InstituteInventors: Yoon Seop CHANG, In Sung JANG, Jae Min SEOL, In Hak JOO, Won Geun CHOI
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Patent number: 9094799Abstract: The present invention relates to a mobile terminal and method for sharing location information between users. The mobile terminal includes a user input unit for receiving destination information of a first user from the first user. A location information input unit receives origin information of the first user from a Global Positioning System (GPS) or a Near-Field Communication (NFC) payment module of public transportation which the first user gets on. A communication unit transmits the origin information and the destination information of the first user to a public transportation information system, and receives movement route information of the first user from the public transportation information system. A location estimation unit estimates a current location of the first user using time required by the first user corresponding to the movement route information.Type: GrantFiled: March 15, 2013Date of Patent: July 28, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seung-Joon Kwon, Won-Geun Choi, Young-Jae Lim, Ji-Sang Park