Abstract: There are provided a memory device and a manufacturing method thereof. The memory device includes: a first stack structure including a plurality of first interlayer insulating layers and a plurality of conductive layers for first word lines, which are alternately stacked; and a second stack structure including a plurality of second interlayer insulating layers and a plurality of conductive layers for second word lines, which are alternately stacked; a first etch stop layer disposed between the first stack structure and the second stack structure; and a plurality of first word line contacts extending to the inside of the first stack structure through the second stack structure and the first etch stop layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.

Abstract: A semiconductor device may include: a gate structure including conductive layers and insulating layers that are alternately stacked. Tapered supports formed in the gate structure layers have a first width at a first level of the layers and a second width smaller than the first width at a second level of the layers. A tapered contact structure is located between the tapered supports in the gate structure having a third width at the first level and a fourth width larger than the third width at the second level. The gate structure taper and the contact structure taper are “mirror images” of each other.

Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a gate stack structure, a channel structure passing through the gate stack structure, and a memory layer between the channel structure and the gate stack structure. A channel layer or a channel pattern, which constitutes the channel structure, includes a structure having a corner or includes a filling type structure and a liner type structure.

Abstract: A semiconductor device includes a gate structure including conductive layers and insulating layers that are alternately stacked. The semiconductor device also includes an insulating core located in the gate structure and including a long axis and a short axis. The semiconductor device further includes a first channel pattern and a second channel pattern surrounding the insulating core and located to face each other along the long axis. The semiconductor device additionally includes a barrier pattern surrounding the first channel pattern and the second channel pattern and having different thicknesses along the long axis and the short axis.

Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a plurality of conductive layers stacked to be spaced apart from each other in a first direction; a channel hole extending in the first direction to penetrate the plurality of conductive layers; two or more channel patterns disposed to be spaced apart from each other along a sidewall of the channel hole; and two or more memory patterns disposed to be spaced apart from each other between the sidewall of the channel hole and the two or more channel patterns, respectively.

Abstract: A semiconductor device includes a supporter including a plurality of stairs, a gate structure including gate lines that are stacked on the supporter, wherein the gate lines include pads, and the pads are disposed over the plurality of stairs, first contact plugs that are connected to the pads, and channel structures that extend through the gate structure.

Abstract: A semiconductor device includes a first gate structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked; an isolation insulating layer located in the first gate structure, the isolation insulating layer including a first line portion extending in a first direction, a plurality of first protrusions protruding from the first line portion towards one side of the first line portion in a second direction, and a plurality of second protrusions protruding from the first line portion towards another side of the first line portion in an opposite direction to the first protrusions, wherein the second direction is orthogonal to the first direction; a plurality of first memory patterns, wherein one of the plurality of first memory patterns surrounds one of the plurality of first protrusions; and a plurality of first passivation patterns, wherein one of the plurality of first passivation patterns is located between the first line portion and one of th

Abstract: A semiconductor device according to an embodiment of the present disclosure includes a first cell area and a second cell area adjacent to each other in a first direction, a support disposed between the first cell area and the second cell area, first gate lines stacked in the first cell area, first pads configured to extend from the first gate lines and configured to protrude upward along a first sidewall of the support, second gate lines stacked in the second cell area, second pads configured to extend from the second gate lines and configured to protrude upward along a second sidewall of the support, and first connection pads configured to extend in the first direction along a third sidewall of the support and configured to electrically connect the first pads with the second pads.

Abstract: The present disclosure includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stack including a plurality of conductive layers stacked to be spaced apart in a first direction, an opening in the stack extending in the first direction and having an elliptical shape in a plan view, and a first channel pattern and a second channel pattern spaced apart from each other in a second direction toward which a major axis of the elliptical shape faces in the opening, the first channel pattern and the second channel pattern extending in the first direction. Each of the first channel pattern and the second channel pattern includes a central portion overlapping with the major axis of the elliptical shape and bent portions extending away from the central portion.

Abstract: A semiconductor device including: a gate structure including stacked gate lines; an insulating core located in the gate structure and including a first long axis and a first short axis; a memory layer surrounding the insulating core; first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and a capping layer located between the first channel pattern and the second channel pattern.

Abstract: A semiconductor device may include: first insulating pillars arranged in a first direction; second insulating pillars arranged alternately with the first insulating pillars and having a first width in the first direction and a second width in a second direction intersecting the first direction, the first width being greater than the second width; first memory cells located between the second insulating pillars and stacked along a first sidewall of each of the first insulating pillars; and second memory cells located between the second insulating pillars and stacked along a second sidewall of each of the first insulating pillars.

Abstract: A memory device and a method of manufacturing the same. The memory device may include a stacked structure including a drain selection line, word lines, and a source selection line that are sequentially stacked, a main plug extending in a vertical direction of the stacked structure, and including a sub-source layer hole in a central portion of an upper area of the main plug, a separation pattern configured to separate the main plug in a vertical direction, and a source line stacked on the stacked structure, and configured to fill the sub-source layer hole.

Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first stack structure including a word line of a first group and select lines of a first group; a second stack structure including select lines of a second group; a first plug in the first stack structure; a second plug connected to the first plug, the second plug being disposed in the second stack structure; a first isolation pattern between the select lines of the first group; and a second isolation pattern between the select lines of the second group.

Abstract: A memory device, and a method of manufacturing the same, includes a stacked structure including gate lines stacked to be spaced apart from each other. The memory device also includes a first channel structure vertical to the gate lines and including a major axis in a first direction. The memory device further includes a second channel structure configured to separate the first channel structure and including a major axis in a second direction orthogonal to the first direction. The first channel structure includes a first memory cell group and a second memory cell group separated from each other by the second channel structure. The second channel structure includes a third memory cell group and a fourth memory cell group separated from each other in the second direction.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a gate stacked structure including conductive layers, each of the conductive layers extending in a first direction and a second direction and including a top surface facing a third direction, wherein the conductive layers are stacked to be spaced apart from each other in the third direction. Also, the semiconductor memory device includes a first channel structure and a second channel structure extending in the third direction to pass through the gate stacked structure and spaced apart from each other in the second direction, a first insulating layer disposed over the gate stacked structure, an etch stop layer disposed over the first insulating layer and including a trench, an insulating material in the trench, and a bit line contact passing through the insulating material.

Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.

Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a stack structure including gate lines stacked to be spaced apart from each other; main plugs arranged to be spaced apart from each other; plug isolation patterns isolating the main plugs into first and second sub-plugs; and a select isolation pattern isolating at least one gate line located between the plug isolation patterns adjacent to each other.

Abstract: A memory device, and a method of manufacturing the same, includes a stack structure and main plugs passing through the stack structure, the main plugs being spaced apart from each other in a first direction. The memory device also includes a separation pattern separating the main plugs in a second direction and a slit pattern separating the stack structure into first and second memory blocks, the slit pattern having an ellipse shape.

Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.