Patents by Inventor Won-Gyu SHIN

Won-Gyu SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915782
    Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Min Lee, Nam Hyung Kim, Dae Jeong Kim, Do Han Kim, Min Su Kim, Deok Ho Seo, Won Jae Shin, Yong Jun Yu, Il Gyu Jung, In Su Choi
  • Patent number: 11824560
    Abstract: An ECC decoder includes a syndrome calculation block, a fast path controller, a KES block, a CSEE block, an UED, and a multiplexer. The KES block includes a plurality of KES-stages to calculate and output an error location/magnitude polynomial of a syndrome outputted from the syndrome calculation block. Each of a second to last KES-stages of the plurality of KES-stages receives the error location/magnitude polynomial from the previous KES-stage to output an error location/magnitude polynomial generated by an additional calculating operation. The additionally calculated error location/magnitude polynomial is not transmitted to the next KES-stage but directly outputted when an error location and an error magnitude are identified by the additionally calculated error location/magnitude polynomial.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: November 21, 2023
    Assignee: SK hynix Inc.
    Inventor: Won Gyu Shin
  • Patent number: 11501832
    Abstract: According to an embodiment, a memory system comprises a resistive memory device configured to perform a read operation and a write operation based on a command and an address, wherein the resistive memory device includes a plurality of banks each including a plurality of memory cells; and a memory controller configured to schedule a request from a host to generate the command and the address, wherein, when a time interval is less than a first time, the memory controller is configured to stop generation of the command and re-schedule the command corresponding to the request, the time interval spanning from a time of generation of a prior write command for a same memory cell to a time of generation of the command generated according to the request.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Won Gyu Shin, Jung Hyun Kwon
  • Publication number: 20220352905
    Abstract: An ECC decoder includes a syndrome calculation block, a fast path controller, a KES block, a CSEE block, an UED, and a multiplexer. The KES block includes a plurality of KES-stages to calculate and output an error location/magnitude polynomial of a syndrome outputted from the syndrome calculation block. Each of a second to last KES-stages of the plurality of KES-stages receives the error location/magnitude polynomial from the previous KES-stage to output an error location/magnitude polynomial generated by an additional calculating operation. The additionally calculated error location/magnitude polynomial is not transmitted to the next KES-stage but directly outputted when an error location and an error magnitude are identified by the additionally calculated error location/magnitude polynomial.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 3, 2022
    Applicant: SK hynix Inc.
    Inventor: Won Gyu SHIN
  • Patent number: 11461022
    Abstract: A memory system may comprise a memory; and a memory controller configured to issue, to the memory, commands scheduled in a first scheme when power consumption of the memory is less than a first threshold and commands scheduled in a second scheme when the power consumption is not less than the first threshold and less than a second threshold, and stop the issuance of the commands to the memory when the power consumption of the memory is not less than the second threshold.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Won Gyu Shin, Jung Hyun Kwon
  • Patent number: 11424765
    Abstract: An error correction code (ECC) decoder includes a syndrome calculation block and a path controller. The syndrome calculation block is configured to perform a syndrome calculation for generating a syndrome from a codeword. The path controller is configured to output data transmitted through first to third paths. The first path is a path for transmitting the codeword to the path controller when no error is detected. The second path includes a single-error decoding logic circuit, and the single-error decoding logic circuit corrects a single error of the codeword to transmit the corrected codeword to the path controller through the second path. The third path includes a multi-error decoding logic circuit, and the multi-error decoding logic circuit corrects at least two errors of the codeword to transmit the corrected codeword to the path controller.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventor: Won Gyu Shin
  • Patent number: 11392457
    Abstract: An error correction method includes performing a first error correction code (ECC) decoding operation of read data outputted from a memory medium and storing the read data outputted from the memory medium into a loop-buffer, in a first operation mode, and performing a second ECC decoding operation of the read data stored in the loop-buffer in a second operation mode.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Won Gyu Shin, Jung Hyun Kwon, Jin Woong Suh, Do Sun Hong
  • Patent number: 11355190
    Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Jung-Hyun Kwon, Won-Gyu Shin, Do-Sun Hong
  • Publication number: 20220147273
    Abstract: A memory system includes: a memory; and a memory controller suitable for issuing a command to the memory and performing a power throttling operation based on a number of read commands and a number of write commands that are issued to the memory for a predetermined time, and ratios of ‘1’ and ‘0’ of write data.
    Type: Application
    Filed: April 8, 2021
    Publication date: May 12, 2022
    Inventors: Won Gyu SHIN, Ju Yeong YOON
  • Publication number: 20220140845
    Abstract: Disclosed is an erasure-based Reed-Solomon code soft-decision decoding method and device, capable of reducing a decoding time while minimizing the effect on error correction performance. The Reed-Solomon code soft-decision decoding device includes an erasure control circuit configured to determine whether a number of errors in a codeword is odd or even, and to provide a key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by a decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.
    Type: Application
    Filed: March 19, 2021
    Publication date: May 5, 2022
    Inventors: Won Gyu SHIN, Jong Sun PARK, Dong Yeob SHIN, Jin Ho JEONG
  • Patent number: 11323138
    Abstract: Disclosed is an erasure-based Reed-Solomon code soft-decision decoding method and device, capable of reducing a decoding time while minimizing the effect on error correction performance. The Reed-Solomon code soft-decision decoding device includes an erasure control circuit configured to determine whether a number of errors in a codeword is odd or even, and to provide a key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by a decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 3, 2022
    Assignees: SK hynix Inc., Korea University Research and Business Foundation
    Inventors: Won Gyu Shin, Jong Sun Park, Dong Yeob Shin, Jin Ho Jeong
  • Publication number: 20220113882
    Abstract: A memory system may comprise a memory; and a memory controller configured to issue, to the memory, commands scheduled in a first scheme when power consumption of the memory is less than a first threshold and commands scheduled in a second scheme when the power consumption is not less than the first threshold and less than a second threshold, and stop the issuance of the commands to the memory when the power consumption of the memory is not less than the second threshold.
    Type: Application
    Filed: April 5, 2021
    Publication date: April 14, 2022
    Inventors: Won Gyu SHIN, Jung Hyun KWON
  • Publication number: 20220108747
    Abstract: According to an embodiment, a memory system comprises a resistive memory device configured to perform a read operation and a write operation based on a command and an address, wherein the resistive memory device includes a plurality of banks each including a plurality of memory cells; and a memory controller configured to schedule a request from a host to generate the command and the address, wherein, when a time interval is less than a first time, the memory controller is configured to stop generation of the command and re-schedule the command corresponding to the request, the time interval spanning from a time of generation of a prior write command for a same memory cell to a time of generation of the command generated according to the request.
    Type: Application
    Filed: March 18, 2021
    Publication date: April 7, 2022
    Inventors: Won Gyu SHIN, Jung Hyun KWON
  • Patent number: 11216335
    Abstract: A memory system includes: a first error detection circuit suitable for generating a first error detection code using host data and a host address which are transferred from a host; a second error detection circuit suitable for generating a second error detection code using system data including one or more host data, a logical address corresponding to one or more host addresses, a physical address corresponding to the logical address and one or more first error detection codes; a third error detection code suitable for generating a third error detection code using the system data, the one or more first error detection codes and the second error detection code; and a first memory suitable for storing the system data, the one or more first error detection codes, the second error detection code and the third error detection code.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Won-Gyu Shin
  • Patent number: 11169915
    Abstract: A memory system includes a memory medium including a plurality of matrices and a plurality of data input/output (I/O) terminals, a row address adding circuit configured to add row address additive values to an input row address for accessing memory cells of the plurality of matrices, and a column address adding circuit configured to add column address additive values to an input column address for accessing to memory cells of the plurality of matrices. The plurality of matrices are configured into a plurality of matrix sub-groups, wherein each matrix sub-group includes matrices accessed through the same data I/O terminal. The row address additive values are different from each other according to the matrix sub-groups, and the column address additive values are different from each other according to the matrix sub-groups.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung Gyu Jeong, Won Gyu Shin
  • Publication number: 20210286674
    Abstract: An error correction method may include performing a first error correction code (ECC) decoding operation of read data outputted from a memory medium and storing the read data outputted from the memory medium into a loop-buffer, in a first operation mode, and performing a second ECC decoding operation of the read data stored in the loop-buffer may be performed in a second operation mode.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Applicant: SK hynix Inc.
    Inventors: Won Gyu SHIN, Jung Hyun KWON, Jin Woong SUH, Do Sun HONG
  • Patent number: 11108412
    Abstract: A memory system includes a Reed-Solomon (RS) decoder, a reliability tracking circuit, and an erasure control circuit. The RS decoder performs an error correction decoding operation of ‘K’-number of symbols outputted from a memory medium. The reliability tracking circuit generates and stores information on a reliability of the symbols, error occurrence possibilities of which are distinguished into a plurality of different levels according to the error correction decoding operation performed by the RS decoder. The erasure control circuit controls the RS decoder such that the symbols are erased in order of the reliability of the symbols from a low reliable symbol to a high reliable symbol and the error correction decoding operation is performed according to the information on the reliability of the symbols stored in the reliability tracking circuit.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventors: Won Gyu Shin, Jin Woong Suh
  • Patent number: 11095310
    Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Won Gyu Shin
  • Patent number: 11048586
    Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Won Gyu Shin, Jung Hyun Kwon, Jin Woong Suh, Do Sun Hong
  • Patent number: 11003531
    Abstract: A memory system includes: a memory device, including a plurality of memory cells, suitable for reading and writing data with a parity bit on a basis of a page; and a memory controller suitable for obtaining an error mask pattern based on compressed data when a number of error bits detected based on the data and the parity bit is equal to or less than a first threshold value and greater than a second threshold value, and controlling to write the compressed data, the parity bit updated based on the compressed data in which the error mask pattern is reflected, compression information on the compressed data and pattern information on the error mask pattern to the page.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung-Hyun Kwon, Do-Sun Hong, Seung-Gyu Jeong, Won-Gyu Shin