Abstract: An error correction code (ECC) decoder includes a syndrome calculation block and a path controller. The syndrome calculation block is configured to perform a syndrome calculation for generating a syndrome from a codeword. The path controller is configured to output data transmitted through first to third paths. The first path is a path for transmitting the codeword to the path controller when no error is detected. The second path includes a single-error decoding logic circuit, and the single-error decoding logic circuit corrects a single error of the codeword to transmit the corrected codeword to the path controller through the second path. The third path includes a multi-error decoding logic circuit, and the multi-error decoding logic circuit corrects at least two errors of the codeword to transmit the corrected codeword to the path controller.

Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

Abstract: A memory system includes a memory medium including a plurality of matrices and a plurality of data input/output (I/O) terminals, a row address adding circuit configured to add row address additive values to an input row address for accessing memory cells of the plurality of matrices, and a column address adding circuit configured to add column address additive values to an input column address for accessing to memory cells of the plurality of matrices. The plurality of matrices are configured into a plurality of matrix sub-groups, wherein each matrix sub-group includes matrices accessed through the same data I/O terminal. The row address additive values are different from each other according to the matrix sub-groups, and the row address additive values are different from each other according to the matrix sub-groups.

Abstract: A memory system includes a Reed-Solomon (RS) decoder, a reliability tracking circuit, and an erasure control circuit. The RS decoder performs an error correction decoding operation of ‘K’-number of symbols outputted from a memory medium. The reliability tracking circuit generates and stores information on a reliability of the symbols, error occurrence possibilities of which are distinguished into a plurality of different levels according to the error correction decoding operation performed by the RS decoder. The erasure control circuit controls the RS decoder such that the symbols are erased in order of the reliability of the symbols from a low reliable symbol to a high reliable symbol and the error correction decoding operation is performed according to the information on the reliability of the symbols stored in the reliability tracking circuit.

Abstract: A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.

Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.

Abstract: A memory device includes a memory region; and an access unit suitable for setting an offset value according to control of an external device, changing, in response to an access command of the external device for a first address of the memory region, the first address into a second address of the memory region based on the offset value, and performing an access operation for the second address.

Abstract: A memory system includes: a first error detection circuit suitable for generating a first error detection code using host data and a host address which are transferred from a host; a second error detection circuit suitable for generating a second error detection code using system data including one or more host data, a logical address corresponding to one or more host addresses, a physical address corresponding to the logical address and one or more first error detection codes; a third error detection code suitable for generating a third error detection code using the system data, the one or more first error detection codes and the second error detection code; and a first memory suitable for storing the system data, the one or more first error detection codes, the second error detection code and the third error detection code.

Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.

Abstract: A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.

Abstract: A memory system includes a memory device comprising first to Nth memory regions, wherein N is a natural number equal to or more than 2, and a memory controller suitable for checking numbers of first logic level data which are contained in first to Nth data groups to be written to the memory device, respectively, and writing the first to Nth data groups to the first to Nth memory regions in order based on the checked numbers.

Abstract: A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.

Abstract: A memory system includes: a first cell array including a plurality of memory cells; and a second cell array including a plurality of memory cells; and an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.

Abstract: A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected memory cell among the resistive memory cells, based on a write command; and a memory controller suitable for providing the write command with the write data to the peripheral circuit and scheduling the write command based on an amount of power consumption calculated depending on the number of either low bits or high bits in the write data.

Abstract: A memory system includes a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit, wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of cell regions. The memory controller controls an operation of the memory device. The memory controller includes a random access memory (RAM) and a cell region management unit. The RAM stores an address mapping table. The address mapping table includes physical block addresses for the plurality of cell regions, logical block addresses mapped with the physical block addresses, and status values corresponding to the physical block addresses. The cell region management unit determines whether there is a first cell region to be cleared among the plurality of cell regions, based on the status values, generates a cell clear command when there is the first cell region, and transmits the cell clear command to the memory device.