Abstract: There is provided a bridgeless power factor correction circuit that corrects a power factor by complementarily switching two switches according to phase of input power without using rectifier bridge diodes. A bridgeless power factor correction circuit according to an aspect of the invention may include: a switching unit having a plurality of switches and alternately switching input AC power; a stabilizing unit rectifying and smoothing the power switched by the switching unit; and a control unit controlling an alternate switching operation between the plurality of switches according to phases of the input power.

Abstract: The example semiconductor memory device may include a memory cell, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation and an output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type. A first example method may include storing at least one data pattern in a storage unit, outputting the stored data within the memory cell in response to a first type of read operation and outputting the at least one data pattern in the storage unit in response to a second type of read operation and blocking access to the memory cell during read operations of the second type.

Abstract: In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory device comprises: a plurality of data input/output drivers; and a plurality of data input/output pads, each connected to a corresponding one of the plurality of data input/output drivers. A first subset of the data input/output pads are connected to respective data input/output pins of a package, and several or all of a remaining subset of the data input/output pads that are not connected to data input/output pins of the package are connected to power pins of the package.

Abstract: A semiconductor memory device that includes a memory cell connected to a wordline and a wordline voltage generator. The wordline voltage generator supplies a first negative voltage to the wordline in a standby state and supplies a second negative voltage that is lower with respect to ground than the first negative voltage to the wordline in a refresh operation. Accordingly, a leakage current generated at a transistor of a memory cell by gate-induced drain leakage (GIDL) is suppressed to enhance the performance of a refresh operation.

Abstract: A memory device including a connector for independently interfacing a host and memory devices using a multimedia card (MMC) protocol is provided. The memory device includes an internal bus and a connector. The internal bus is configured to receive a command or data from the host via a plurality of input/output pins. The connector is electrically connected with the internal bus and connected with another memory device, which interfaces with the host through the internal bus using the MMC protocol.

Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: A method of transmitting data from a flash memory device to a host includes: detecting whether the data includes an error or not; performing an error correction operation for correcting the data having the error when the error exists in the data; and sequentially storing the data having the error and a plurality of subsequent read data without outputting. The storing of the data is performed during the performing of the error correction operation.

Abstract: There are provided a semiconductor memory device and a method for testing the same, in which when a plurality of semiconductor memory devices are under test, tester equipment can detect which one of the semiconductor memory devices fails without a separate fail memory. The semiconductor memory device with a memory cell array includes a comparing circuit configured to compare data read after having been written for parallel bit testing with each other and outputting comparison result data; and a storage and output unit configured to latch, as pass/fail data, the comparison result data output from the comparing circuit, simultaneously output the latched comparison result data via a plurality of outputs when an enable signal is activated, and simultaneously output independently applied parallel bit test comparison data via the plurality of outputs when the enable signal is not activated.

Abstract: A flash memory card including a main memory core, a removable supplementary memory core, and a controller operating to control the main and supplementary memory cores. The supplementary memory core includes a plurality of memory cores and is replaceable.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: An apparatus and method for transmitting packet data in a high-speed packet transmitting mobile communication system. In the packet data transmitting apparatus, a packet data channel generator processes packet data to be transmitted on a packet data channel, a preamble signal generator transmits a preamble signal according to a gain of the packet data channel, a select signal generator generates a select signal to transmit the preamble signal a predetermined time before transmitting the packet data, and a multiplexer outputs the preamble signal upon receipt of the select signal and the packet data in time division when the select signal is not received.

Abstract: A semiconductor memory device includes both a data redundancy memory cell array and a local redundancy memory cell array. Cells of the data redundancy memory cell array and/or cells the local redundancy memory cell arrays may be substituted for one or more defective cells of a normal memory cell array, depending on the number of defects generated in the normal memory cell array. An embodiment of a semiconductor memory device may include a plurality of normal memory blocks, each normal memory block comprising a normal memory cell array and a local redundancy memory cell array, at least one data line redundancy memory block, each data line redundancy memory block comprising a data redundancy memory cell array, and a redundancy controller to substitute columns of the data line redundancy memory cell array for some columns of at least two columns in each normal memory cell array, and to substitute columns of the local redundancy memory cell array for the remaining columns of the at least two columns.

Abstract: An apparatus for controlling black stretch includes a black stretching unit, an offset adjusting unit and an output unit. The black stretching unit performs black stretch processing on a video signal less than or equal to the maximum value of a black stretch control range in response to a slope of black stretch. The slope of black stretch corresponds to a region between a minimum value and a maximum value of the black stretch control range. The offset adjusting unit adjusts an offset of the black-stretched video signal. The output unit outputs an output video signal corresponding to the offset-adjusted video signal when the offset-adjusted video signal has a positive value in a region less than or equal to the minimum value, and outputs the output video signal corresponding to 0 when the offset-adjusted video signal has a negative value in the region less than or equal to the minimum value.

Abstract: A memory card including a pad, a drive circuit activating the pad in accordance With an input signal, and a controller regulating a drive voltage level and a drive point of an output signal generated from the drive circuit in accordance with a voltage level of the output signal of the drive circuit. The controller may include a delay circuit, generating a second clock signal by delaying a first clock signal provided from an external source and generating a second clock signal from the first clock signal. The controller may further include a detection circuit capturing the voltage level of the output signal of the drive circuit as a first detection voltage in sync with the first clock signal and capturing the voltage level of the output signal of the drive circuit as a second detection voltage in sync with the second dock signal.

Abstract: Computer systems and related methods are provided for managing connections to storage devices. The computer system includes a connector and a register. The connector includes a plurality of pins configured to be removably connected to a first storage device and to a second storage device. A first pin of the connector carries a signal that indicates when the connector is connected to the first storage device, and a second pin carries a signal that indicates when the connector is connected to the second storage device. The register stores connection information that indicates whether the first storage device and/or the second storage device are connected to the connector.

Abstract: A system determination method and apparatus are provided which can again acquire a system in a shortened time when a mobile terminal has lost an acquired system in a weak electric field area. When power is applied, the terminal reads system information of an acquisition table of a preferred roaming list and system information of a most recently used (MRU) table from a memory and generates a search list using the read information. The terminal determines whether a ping counter is applied through the generated search list. If the ping counter is applied, the terminal determines whether a ping counter value is equal to a maximum ping counter value. If the ping counter value is equal to the maximum ping counter value, the terminal initializes the ping counter value, selects a system from the MRU table and makes a system acquisition attempt.

Abstract: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include a memory cell configured to store data, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation and an output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type. A first example method may include storing at least one data pattern in a storage unit, outputting the stored data within the memory cell in response to a first type of read operation and outputting the at least one data pattern in the storage unit in response to a second type of read operation and blocking access to the memory cell during read operations of the second type.

Abstract: A method for preparing powder granules by a liquid condensation process comprising preparing a slurry by mixing powders, a binding agent and a binding agent soluble solvent, dropping the slurry to a binding agent insoluble solvent to fix the binding agent so that the binding agent can not be released to a surface of a droplet of the slurry, coagulating the droplet by solvent exchange between the soluble solvent inside the droplet and the insoluble solvent at the surface of the droplets, and separating the coagulated droplet from the insoluble solvent, drying it and completely removing a residual solvent.

Abstract: In the DC/DC converter, a switching part has first and second switches serially connected from a power supply to a ground. The first and second switches switch on/off in response to first and second switching signals having a fixed frequency. The first switching signal has a phase level that does not overlap a corresponding phase level of the second switching signal. A transformer transforms a voltage applied to a first winding into a second winding in response to switching operation of the switching part, and resonates by an inductor and a capacitor of the first winding. Also, a rectifier includes a rectifying diode for rectifying the voltage from the transformer into a direct voltage. A feedback circuit detects the voltage outputted via the rectifier. Additionally, a controller controls pulse width of the first and second switching signals in a PWM mode according to the voltage detected by the feedback circuit.