Abstract: Disclosed herein are an asset creation method using a covariance matrix-based parallel network and an apparatus for the same. The asset creation method includes simultaneously performing segmentation and position information identification on a target object to be assetized from a video received from a user terminal based on a parallel network including a three-dimensional (3D) semantic segmentation network and a Long Short-Term Memory (LSTM) network, and generating a 3D video feature of the target object from results of the segmentation and the position information identification based on a covariance matrix, and creating an asset in conformity with the 3D video feature.

Abstract: A method and an apparatus for optimizing communication of mobile base stations are provided. The method responds to an optimization problem of maximizing a sum rate of transmission and generates a QUBO model capable of quantum computing to rapidly enable optimal resource allocation through quantum annealing.

Abstract: This application relates to an optical sensor element. In one aspect, the optical sensor element includes a graphite column including one or more graphite rods. The optical sensor element may also include one or more first graphene layers partly or entirely covering each of both ends of the graphite column. The optical sensor element may further include one or more second graphene layers partly or entirely covering the outer circumferential surface of the graphite column. This application also relates to an optical sensor for measuring the concentration of a greenhouse gas and the optical sensor includes the optical sensor element.

Abstract: Disclosed are a leaf-shaped pastry sheet dough composition with rolled-in margarine for baking and a method of preparing a chocolate pastry using the same. More specifically, the method includes rolling-in margarine with 0% butterfat to prepare pastry dough for baking, molding the dough into a predetermined leaf shape, topping the dough with a pre-mix of a maltose powder and powdered sugar at a ratio of 7:3 to impart exterior gloss to the baked pastry, baking the resulting dough, and coating the bottom of the baked pastry confectionery with tempered chocolate. This process was first attempted in the chocolate pastry confectionery with a long shelf life of one month or more in Korea.

Abstract: A crime type inference system based on text data, may include: a keywords dictionary construction unit configured to receive crime source data, and generate a crime type keywords dictionary by extracting crime keywords; a data set construction unit configured to generate a dataset for crime type learning by using the crime source data and the keywords dictionary; a crime type prediction model training unit configured to generate a crime type prediction model by using the dataset, and train the crime type prediction model; and a crime type inference unit configured to infer a crime type by using new crime data.

Abstract: Disclosed is an apparatus for generating a depth map using a monocular image. The apparatus includes: a deep convolution neural network (DCNN) optimized based on an encoder and decoder architecture. The encoder extracts one or more features from the monocular image according to the number of provided feature layers, and the decoder calculates displacements of mismatched pixels from the features extracted from different feature layers, and generates the depth map for the monocular image.

Abstract: Systems and methods are provided for a memory device that includes a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to reset taps of a DFE. The memory device also includes an input buffer. The input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. The input buffer also includes a DFE reset branch configured to reset the taps for the DFE based on the DFE reset signal. Moreover, resetting the taps using the DFE reset branch does not reset output data of the data branch.

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

Abstract: Disclosed herein are a method for making a montage based on a dialogue and an apparatus using the same. The method includes extracting a feature for making a montage based on the dialogue between at least one inquirer and at least one respondent, generating a facial feature image based on the feature, and making a montage based on the facial feature image.

Abstract: A semiconductor device includes an interface configured to receive clock signals and data signals. The interface includes a dual-tail latch. The dual-tail latch includes a sensing stage configured to sense and to amplify a differential voltage between at least a portion of the data signals and another signal. The sensing stage includes a first node and a second node between which the amplified differential voltage is output from the sensing stage. The dual-tail latch also includes a latch stage configured to latch a first latched value and a second latched value based at least in part on the amplified differential voltage. Moreover, the differential voltage is based at least in part on a previous first value and a previous second value from the latch stage fed back to the sensing stage.

Abstract: A semiconductor device includes a pair of transistors configured to implement buffering of input data to outputs. The semiconductor device also includes a first transistor configured to receive a common-mode of the outputs at a gate terminal of the first transistor. The semiconductor device also includes a current source configured to control a tail current from the pair of transistors. Additionally, the semiconductor device includes a second transistor configured to adjust the tail current based at least in part on changes in a reference voltage used by the pair of transistors to buffer the input data. Furthermore, the semiconductor device includes a third transistor configured to adjust the tail current based at least in part on changes in locally generated reference voltage based at least in part on a process and temperature variations.

Abstract: Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

Abstract: A method of providing a service for a conversation with a virtual character replicating a deceased person is provided. The method of the present disclosure includes predicting a response message of a virtual character replicating a deceased person in response to a message input by a user, generating a speech corresponding to an oral utterance of the response message on the basis of speech data of the deceased person and the response message, and generating a final video of the virtual character uttering the response message on the basis of a driving video guiding the movement of the virtual character and the speech.

Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. A reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Abstract: A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.

Abstract: Disclosed is a mutant strain having improved aromatic amino acid production capability as a result of the inactivation or weakening of activity of asparaginase which is expressed by ansB gene.

Abstract: The present disclosure relates to a double sealing check valve for a rice cooker, and more particularly, to a double sealing check valve for a rice cooker that prevents water vapor mixed with rice water and grain dregs from entering the check valve and maintains airtightness during cooking in an automatic water supply type pressure cooker that automatically supplies water and performs pressure cooking.

Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a semiconductor package may include a substrate having a first plurality of substrate bond pads and a second plurality of substrate bond pads, and a semiconductor die having a first plurality of die bond pads and a second plurality of die bond pads. Each die bond pad, included in the first plurality of die bond pads, may be connected to a corresponding substrate bond pad, included in the first plurality of substrate bond pads, using bump bonding, and each die bond pad, included in the second plurality of die bond pads, may be connected to a corresponding substrate bond pad, included in the second plurality of substrate bond pads, using wire bonding.

Abstract: A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.