Patents by Inventor Won-Mo Park
Won-Mo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240117941Abstract: A hydrogen storage system is disclosed and includes a storage unit including a plurality of unit storage containers, in which metal hydride materials are respectively provided in an interior thereof and which are connected to each other in parallel, and a thermal fluid line defining a thermal fluid passage, which passes via the plurality of unit storage containers continuously and through which a thermal fluid flows for heating or cooling the unit storage containers, thereby enhancing a storage performance and an efficiency of the hydrogen.Type: ApplicationFiled: March 10, 2023Publication date: April 11, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Ji Hye Park, Won Jung Kim, Kyung Moon Lee, Dong Hoon Nam, Young Jin Cho, Byeong Soo Shin, Ji Hoon Lee, Suk Hoon Hong, Hoon Mo Park, Yong Doo Son
-
Publication number: 20240117930Abstract: A hydrogen storage device includes a storage container having an accommodation space in an interior thereof, a first metal hydride material provided in the interior of the storage container and that stores hydrogen, and a second metal hydride material provided in the interior of the storage container and that stores the hydrogen at a pressure that is different from that of the first metal hydride material. An advantageous effect of restraining an excessive rise of a pressure of the storage container and enhancing safety and reliability may be obtained.Type: ApplicationFiled: March 10, 2023Publication date: April 11, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Ji Hye Park, Won Jung Kim, Kyung Moon Lee, Dong Hoon Nam, Young Jin Cho, Byeong Soo Shin, Ji Hoon Lee, Suk Hoon Hong, Hoon Mo Park, Yong Doo Son
-
Publication number: 20210217782Abstract: A display device includes gate lines disposed on a substrate in a first direction, data lines disposed on the substrate in a second direction crossing the first direction, the data lines being insulated from the gate lines, a first insulating film disposed between the data lines, a second insulating film disposed on the data lines and the first insulating film, and a first electrode disposed on the second insulating film. The first insulating film does not overlap the data lines in a direction perpendicular to the substrate.Type: ApplicationFiled: September 28, 2020Publication date: July 15, 2021Applicant: Samsung Display Co., LTD.Inventors: Seong-Min KIM, Won Mo PARK, Jin Koo CHUNG, Kyung Soo JANG, Min Hyun JIN, Beohm Rock CHOI
-
Patent number: 11048370Abstract: There is provided a display device. The display device includes a display panel for displaying an image on a front surface thereof and a pressure sensor disposed on a rear surface of the display panel to sense touch pressure of a user. The pressure sensor includes a first sensing electrode and a second sensing electrode insulated from each other to form capacitance. The first sensing electrode is printed onto the rear surface of the display panel.Type: GrantFiled: November 17, 2017Date of Patent: June 29, 2021Inventors: Gun Woo Ko, Won Mo Park, Hye Kyung Park
-
Patent number: 11010009Abstract: There is provided a display device. The display device includes a display panel for displaying an image on a front surface thereof and a pressure sensor disposed on a rear surface of the display panel to sense touch pressure of a user. The pressure sensor includes a first sensing electrode and a second sensing electrode insulated from each other to form capacitance. The first sensing electrode is printed onto the rear surface of the display panel.Type: GrantFiled: November 17, 2017Date of Patent: May 18, 2021Inventors: Gun Woo Ko, Won Mo Park, Hye Kyung Park
-
Publication number: 20180188849Abstract: There is provided a display device. The display device includes a display panel for displaying an image on a front surface thereof and a pressure sensor disposed on a rear surface of the display panel to sense touch pressure of a user. The pressure sensor includes a first sensing electrode and a second sensing electrode insulated from each other to form capacitance. The first sensing electrode is printed onto the rear surface of the display panel.Type: ApplicationFiled: November 17, 2017Publication date: July 5, 2018Inventors: Gun Woo Ko, Won Mo Park, Hye Kyung Park
-
Patent number: 9935133Abstract: A display device includes: a first substrate comprising a display area including a plurality of pixels, and a peripheral area around the display area; a plurality of driving signal transmission lines on the first substrate and arranged in the peripheral area; a first insulating layer on the first substrate and arranged under the plurality of driving signal transmission lines; and a second insulating layer on a portion of the plurality of driving signal transmission lines and arranged in the display area, and the first insulating layer includes a trench between two driving signal transmission lines adjacent to each other among the plurality of driving signal transmission lines, and an edge portion of the second insulating layer overlaps the trench.Type: GrantFiled: March 17, 2016Date of Patent: April 3, 2018Assignee: Samsung Display Co., Ltd.Inventors: Deuk Jong Kim, Hyo Jin Kim, Won Mo Park
-
Patent number: 9929225Abstract: A display device includes a substrate, first through fourth metal wires, first and second insulating layers, and a compensation pattern. The first metal wire is positioned on the substrate and extends in a first direction. The first insulating layer is positioned on the first metal wire and the substrate. The second metal wire is positioned on the first insulating layer, extends in the first direction, and is adjacent to the first metal wire. The second insulating layer is positioned on the first insulating layer and the second metal wire. The compensation pattern is positioned on the second insulating layer and is disposed between the first metal wire and the second metal wire. The third metal wire and the fourth metal wire are positioned on the second insulating layer and extend in a second direction that is different from the first direction.Type: GrantFiled: April 27, 2016Date of Patent: March 27, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Won Mo Park, Young Su Kim
-
Patent number: 9660011Abstract: Provided is an organic light emitting diode display device, including a pixel substrate including a pixel unit displaying an image and a peripheral unit surrounding the pixel unit; a first insulating layer covering the pixel substrate; a fanout line on the first insulating layer of the peripheral unit; a second insulating layer covering the first insulating layer and the fanout line; an etching prevention member on the second insulating layer of the peripheral unit and preventing overetching of the second insulating layer; a third insulating layer covering the second insulating layer; a peripheral potential voltage line on the third insulating layer of the peripheral unit and transferring a potential voltage; a passivation layer covering the third insulating layer; and an organic light emitting diode on the passivation layer of the pixel unit, in which the etching prevention member overlaps with the fanout line and the peripheral potential voltage line.Type: GrantFiled: April 30, 2015Date of Patent: May 23, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Deuk Jong Kim, Won Mo Park, Yong Ho Yang
-
Publication number: 20170141175Abstract: A display device includes a substrate, first through fourth metal wires, first and second insulating layers, and a compensation pattern. The first metal wire is positioned on the substrate and extends in a first direction. The first insulating layer is positioned on the first metal wire and the substrate. The second metal wire is positioned on the first insulating layer, extends in the first direction, and is adjacent to the first metal wire. The second insulating layer is positioned on the first insulating layer and the second metal wire. The compensation pattern is positioned on the second insulating layer and is disposed between the first metal wire and the second metal wire. The third metal wire and the fourth metal wire are positioned on the second insulating layer and extend in a second direction that is different from the first direction.Type: ApplicationFiled: April 27, 2016Publication date: May 18, 2017Inventors: WON MO PARK, YOUNG SU KIM
-
Publication number: 20160276373Abstract: A display device includes: a first substrate comprising a display area including a plurality of pixels, and a peripheral area around the display area; a plurality of driving signal transmission lines on the first substrate and arranged in the peripheral area; a first insulating layer on the first substrate and arranged under the plurality of driving signal transmission lines; and a second insulating layer on a portion of the plurality of driving signal transmission lines and arranged in the display area, and the first insulating layer includes a trench between two driving signal transmission lines adjacent to each other among the plurality of driving signal transmission lines, and an edge portion of the second insulating layer overlaps the trench.Type: ApplicationFiled: March 17, 2016Publication date: September 22, 2016Inventors: Deuk Jong KIM, Hyo Jin KIM, Won Mo PARK
-
Publication number: 20160104757Abstract: Provided is an organic light emitting diode display device, including a pixel substrate including a pixel unit displaying an image and a peripheral unit surrounding the pixel unit; a first insulating layer covering the pixel substrate; a fanout line on the first insulating layer of the peripheral unit; a second insulating layer covering the first insulating layer and the fanout line; an etching prevention member on the second insulating layer of the peripheral unit and preventing overetching of the second insulating layer; a third insulating layer covering the second insulating layer; a peripheral potential voltage line on the third insulating layer of the peripheral unit and transferring a potential voltage; a passivation layer covering the third insulating layer; and an organic light emitting diode on the passivation layer of the pixel unit, in which the etching prevention member overlaps with the fanout line and the peripheral potential voltage line.Type: ApplicationFiled: April 30, 2015Publication date: April 14, 2016Inventors: Deuk Jong KIM, Won Mo PARK, Yong Ho YANG
-
Patent number: 8883622Abstract: A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.Type: GrantFiled: March 7, 2012Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Won-mo Park, Min-wk Hwang, Hyun-chul Kim
-
Patent number: 8759945Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.Type: GrantFiled: April 7, 2011Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim, Ho-Ju Song
-
Publication number: 20140141577Abstract: A method of manufacturing a thin film transistor array panel includes forming a semiconductor on a substrate, forming a gate insulating layer on the semiconductor, forming a sacrificial layer including an opening on the gate insulating layer, forming a copper layer on the sacrificial layer, the copper layer filling the opening, forming a gate wiring by polishing the copper layer by chemical mechanical polishing until the sacrificial layer is exposed, removing the sacrificial layer, forming a source region and a drain region by doping conductive impurities on the semiconductor by using the gate wiring as a mask, forming a first interlayer insulating layer covering the gate wiring, and forming a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the first interlayer insulating layer.Type: ApplicationFiled: October 17, 2013Publication date: May 22, 2014Applicant: SAMSUNG DISPLAY CO., LTD.Inventor: Won-Mo PARK
-
Patent number: 8633565Abstract: A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.Type: GrantFiled: July 21, 2010Date of Patent: January 21, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Ju Song, Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim
-
Publication number: 20120231619Abstract: A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.Type: ApplicationFiled: March 7, 2012Publication date: September 13, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Won-mo Park, Min-wk Hwang, Hyun-chul Kim
-
Publication number: 20110298086Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.Type: ApplicationFiled: April 7, 2011Publication date: December 8, 2011Inventors: Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim, Ho-Ju Song
-
Patent number: 8058678Abstract: Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.Type: GrantFiled: August 7, 2009Date of Patent: November 15, 2011Assignee: Samsunge Electronics Co., Ltd.Inventors: Gil-Sub Kim, Won-Mo Park, Seong-Ho Kim, Dong-Kwan Yang
-
Patent number: 8043925Abstract: A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.Type: GrantFiled: November 6, 2009Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-kwan Yang, Seong-ho Kim, Won-mo Park, Gil-sub Kim