Abstract: Provided is an ultra large-width coating device applied to a consecutive process. More particularly, the present invention relates to a coating device capable of maximizing productivity by consecutively manufacturing a large-width film without reducing physical properties of the manufactured film by overcoming a problem in that a coating width is limited during a coating process using the existing contact type coating roller, and a method for manufacturing an ultra large-width membrane using the same.

Abstract: An antenna device according to an embodiment of the present invention includes a dielectric layer, an antenna unit disposed on a top surface of the dielectric layer, the antenna unit including a radiator and a transmission line connected to the radiator, a dummy electrode separated from the antenna unit on the top surface of the dielectric layer, the dummy electrode at least partially surrounding the antenna unit, and a blocking pattern arranged around the antenna unit in the dummy electrode. Radiation interruption from the dummy electrode is prevented by the blocking pattern to improve radiation reliability.

Abstract: Disclosed is a cathode for a lithium secondary battery, which has a coating layer formed on an edge portion of a cathode plate, a method of manufacturing the cathode, and a lithium secondary battery including the cathode. The cathode includes a cathode plate and a coating layer formed at an edge portion of the cathode plate, in which the cathode plate includes a cathode current collector provided with cathode tab and a cathode active material laminated on at least one surface of the cathode current collector, and the coating layer includes a conductive polymer layer and an insulating coating layer.

Abstract: An aerosol generating device may include a heater configured to heat an aerosol generating material, a battery configured to supply power to the heater, and a controller. In addition, the aerosol generating device may further include a user input detection sensor configured to receive a user's input and a pressure detection sensor configured to sense pressure. The controller may, in response to the user's input being sensed by using the user input detection sensor, obtain an initial pressure sensing value by using the pressure detection sensor. In addition, the controller may determine a reference pressure value based on the initial pressure sensing value and determine whether a puff of the aerosol generating device has occurred based on the reference pressure value.

Abstract: The present application relates to a novel strain of the genus Schizochytrium (Schizochytrium sp.) and a method of producing polyunsaturated fatty acids by using the same. According to one aspect, novel microalgae of the genus Schizochytrium have a high content of fat in biomass, and particularly, a high content of polyunsaturated fatty acids such as docosahexaenoic acid (DHA) and eicosapentaenoic acid (EPA), and therefore, the microalgae, and biomass or bio-oil prepared therefrom, may be useful as a feed source or the like.

Abstract: Provided are a separator coating composition for a secondary battery including inorganic particles and a silane salt compound having a specific structure, a separator using the same, and an electrochemical device including the same. Specifically, a separator coating composition for a secondary battery which implements adhesion between an inorganic material layer and a porous substrate without including an acid/polymer-based organic binder in a coating composition for forming the inorganic material layer on one or both surfaces of the porous substrate and does not need a separate dispersing agent for dispersing the inorganic particles, a separator manufactured using the same, and an electrochemical device including the separator are provided.

Abstract: The present disclosure provides an operation apparatus operating based on the Winograd algorithm for multiplying a first matrix by a second matrix to generate a third matrix, including a plurality of second accumulated value calculation units, of which one second accumulated value calculation unit is configured to accumulate second multiplication values obtained by multiplying each of paired element values of the second matrix, a second accumulated value output unit outputting selecting and outputting one of output values of adjacent second accumulated value calculation unit and an accumulated second multiplication value as a second accumulated value, a third accumulated value output unit including a plurality of third accumulated value calculation units and generating third accumulated value, and one or more row element value calculation units, of which one row element value calculation unit is configured to accumulate first matrix element multiplication values obtained by multiplying each of the paired elem

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

Abstract: A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

Abstract: A command processing method and processor performing the method are provided. The method includes: determining a priority of a variable of a program based on a usage frequency of the variable; determining an address at which a value of the variable is stored in a memory based on the priority of the variable; and generating a command that relates to the variable based on a bit string length of the address.

Abstract: Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.

Abstract: A reconfigurable processor based on mini-cores (MCs) includes a plurality of MCs, each MC of the MCs including a group of function units (FUs), the group of FUs having a capability of executing a loop iteration independently. The MCs include a first MC configured to execute a first loop iteration, and a second MC configured to execute a second loop iteration.

Abstract: A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.

Abstract: An apparatus for processing an invalid operation in a prologue and/or an epilogue of a loop includes a register file including a first region for storing a data validity value indicating whether data is valid or invalid, and a second region for storing the data; and a functional unit configured to determine whether an operation is valid or invalid based on a value of a first region of each of one or more input sources received from the register file, and output a destination including a value based on the value of the first region of each of the input sources.

Abstract: A technology for executing an external operation from a software-pipelined loop is provided. Code performance efficiency can be improved by overlapping the execution of the external operations of the loop and the iterations of the loop.

Abstract: A modulo scheduling method including calculating at least two candidate initiation intervals between adjacent iterations, searching for schedules of the instructions in parallel by using the candidate initiation intervals, and selecting a schedule determined to be valid from among the searched schedules.

Abstract: A command processing method and processor performing the method are provided. The method includes: determining a priority of a variable of a program based on a usage frequency of the variable; determining an address at which a value of the variable is stored in a memory based on the priority of the variable; and generating a command that relates to the variable based on a bit string length of the address.

Abstract: A method for scheduling loop processing of a reconfigurable processor includes generating a dependence graph of instructions for the loop processing; mapping a first register file of the reconfigurable processor on an arrow indicating inter-iteration dependence on the dependence graph; and searching for schedules of the instructions based on the mapping result.

Abstract: A scheduler and scheduling method perform scheduling for a reconfigurable architecture. The scheduling, performed by the scheduler, includes path information extracting including extracting direct path information and indirect path information between functional units in a reconfigurable array complying with predefined architecture requirements, based on architecture information of the reconfigurable array, command selecting including selecting a command from a data flow graph (DFG) showing commands to be executed by the reconfigurable array, and scheduling including scheduling the selected command based on the extracted direct path information and indirect path information.