Patents by Inventor Woo-Jin Cho

Woo-Jin Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180108684
    Abstract: A method for manufacturing a display device includes forming a first gate metal wire on a substrate, forming a first insulation layer that covers the first gate metal wire, forming a second gate metal wire on the first insulation layer, forming a second main insulation layer that covers the second gate metal wire, forming a second auxiliary insulation layer on the second main insulation layer, forming an exposed portion of an upper surface of the second main insulation layer by polishing the second auxiliary insulation layer, and forming a first data metal wire on the second main insulation layer and the second auxiliary insulation layer.
    Type: Application
    Filed: September 13, 2017
    Publication date: April 19, 2018
    Inventors: Hyun Jin CHO, Joon-Hwa BAE, Byoung Kwon CHOO, Byung Hoon KANG, Kwang Suk KIM, Woo Jin CHO, Jun Hyuk CHEON
  • Publication number: 20180099904
    Abstract: A method of manufacturing strengthened glass includes: preparing glass including blocking patterns on a surface thereof, portions of the surface exposed between the blocking patterns; forming a metal particle layer on the portions of the surface of the glass exposed between the blocking patterns; removing the blocking patterns from the surface of the glass, to maintain the metal particle layer on the surface of the glass; with the metal particle layer maintained on the surface of the glass, etching the surface of the glass using the metal particle layer as an etching mask to form an etched surface of the glass, such etched surface including protruding patterns spaced apart from each other by portions of a common reference surface; and chemically strengthening the etched surface of the glass at the protruding patterns and at the reference surface.
    Type: Application
    Filed: May 11, 2017
    Publication date: April 12, 2018
    Inventors: Jeong Woo PARK, Hyun Joon OH, Woo Jin CHO, Seung Ho KIM, Hee Kyun SHIN, Jong Hoon YEUM, Hoi Kwan LEE
  • Publication number: 20180059454
    Abstract: A cover window is disclosed. The cover window may include a first surface, a second surface opposite the first surface, a first polishing surface extending from an end of the first surface along a first direction, the first polishing surface having a first inclination angle, and a second polishing surface extending from an end of the second surface along a second direction, the second polishing surface having a second inclination angle. The first polishing surface and the second polishing surface may be asymmetric with respect to a center plane, the center plane passing through a center of the cover window and in parallel with the first surface.
    Type: Application
    Filed: July 28, 2017
    Publication date: March 1, 2018
    Inventors: Hee-Kyun SHIN, Eun-Kyung YEON, Seung-Ho KIM, Hyun-Joon OH, Woo-Jin CHO
  • Publication number: 20180043501
    Abstract: A substrate polishing system includes: a polishing machine and a substrate transporter. The polishing machine includes: a lower surface plate to which a substrate is mounted, and an upper surface plate which faces the lower surface plate and polishes the substrate in cooperation with the lower surface plate, the upper surface plate having a larger area than the substrate mounted on the lower surface plate. The substrate transporter is adjacent to the polishing machine and commonly transports the substrate to and from the polishing machine in a first direction, attaches the substrate to the lower surface plate before polishing thereof, and separates from the lower surface plate the substrate after polishing thereof.
    Type: Application
    Filed: July 31, 2017
    Publication date: February 15, 2018
    Inventors: Hyun Jin CHO, Joon-Hwa BAE, Byoung Kwon CHOO, Byung Hoon KANG, Jun Hyuk CHEON, Jeong-Hye CHOI, Young Ho JEONG, Woo Jin CHO
  • Publication number: 20180047762
    Abstract: A method of manufacturing a transistor display panel and a transistor display panel, the method including forming a polycrystalline silicon layer on a substrate; forming an active layer by patterning the polycrystalline silicon layer; forming a first insulating layer covering the substrate and the active layer; exposing the active layer by polishing the first insulating layer using a polishing apparatus; and forming a second insulating layer that contacts the first insulating layer and the active layer, wherein exposing the active layer by polishing the first insulating layer includes coating a first slurry on a surface of the first insulating layer, the first slurry reducing a polishing rate of the active layer.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 15, 2018
    Inventors: Joon-Hwa BAE, Byoung Kwon CHOO, Byung Hoon KANG, Woo Jin CHO, Hyun Jin CHO, Jun Hyuk CHEON, Jee-Hyun LEE
  • Publication number: 20180037684
    Abstract: The present invention relates to a neodymium compound represented by Formula 1 and a catalyst for diene polymerization including the same.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 8, 2018
    Inventors: Hyo Jin BAE, Kyoung Hwan OH, Sae Young YUN, Jeong Heon AHN, Woo Jin CHO
  • Publication number: 20180030174
    Abstract: The present invention provides a catalyst composition including a functionalizing agent of the following Formula 1 together with a rare earth metal compound, an alkylating agent, and a halogen compound, having good catalytic activity and polymerization reactivity and useful for the preparation of a conjugated diene-based polymer having high linearity and excellent processability, and a conjugated diene-based polymer prepared using the catalyst composition. (X1)a—Sn—(X2)4-a,??[Formula 1] In Formula 1, a, X1, and X2 are the same as defined in the disclosure.
    Type: Application
    Filed: June 24, 2016
    Publication date: February 1, 2018
    Applicant: LG Chem, Ltd.
    Inventors: Suk Youn Kang, Soo Young Choi, Woo Jin Cho, Suk Joon Yoo, Jeong Heon Ahn, Jin Sook Ryu
  • Publication number: 20180030173
    Abstract: The present invention provides a catalyst composition including a functionalizing agent of the following Formula 1 together with a rare earth metal compound, an alkylating agent, and a halogen compound, having good catalytic activity and polymerization reactivity and useful for the preparation of a conjugated diene-based polymer having high linearity and excellent processability, and a conjugated diene-based polymer prepared using the catalyst composition. (X1)a-M1-([Y-M2-(X2)n-1])m-a??[Formula 1] In Formula 1, a, m, n, M1, M2, X1, X2 and Y are the same as defined in the disclosure.
    Type: Application
    Filed: June 24, 2016
    Publication date: February 1, 2018
    Applicant: LG Chem, Ltd.
    Inventors: Suk Youn Kang, Hyo Jin Bae, Kyoung Hwan Oh, Woo Jin Cho, Jeong Heon Ahn, Sung Hyun Park
  • Publication number: 20170275401
    Abstract: The present invention provides 1,4-cis polybutadiene having high linearity with an ?S/R value of 1 or greater at 100° C., and accordingly, is capable of reducing resistance properties, particularly rolling resistance, and greatly enhancing fuel efficiency properties when used in a rubber composition.
    Type: Application
    Filed: November 18, 2015
    Publication date: September 28, 2017
    Applicant: LG Chem, Ltd.
    Inventors: Kyoung Hwan Oh, Won Hee Kim, Hyo Jin Bae, Jeong Heon Ahn, Woo Jin Cho, Suk Youn Kang
  • Publication number: 20170275391
    Abstract: The present invention provides a catalyst composition exhibiting, by including a lanthanide rare earth element-containing compound; modified methylaluminoxane; a halogen compound; and an aliphatic hydrocarbon-based solvent, excellent catalytic activity even with a small main catalyst amount, capable of preparing a conjugated diene-based polymer having excellent catalytic activity and thereby having high cis-1,4-bond content ratio, high linearity, and narrow molecular weight distribution, and capable of reducing polymerization reaction time, and a method for preparing the same.
    Type: Application
    Filed: November 18, 2015
    Publication date: September 28, 2017
    Applicant: LG Chem, Ltd.
    Inventors: Won Hee Kim, Hyo Jin Bae, Jeong Heon Ahn, Hee Jung Jeon, Kyoung Hwan Oh, Woo Jin Cho, Suk Youn Kang
  • Publication number: 20170240669
    Abstract: The present invention provides a method for preparing a conjugated diene-based polymer including preparing a mixture of a molecular weight modifier and a conjugated diene-based monomer; and polymerization reacting the mixture using a catalyst composition including a lanthanide rare earth element-containing compound, modified methylaluminoxane, a halogen compound and an aliphatic hydrocarbon-based solvent, and therefore, capable of preparing a conjugated diene-based polymer having a high cis-1,4-bond content ratio, high linearity and narrow molecular weight distribution.
    Type: Application
    Filed: November 18, 2015
    Publication date: August 24, 2017
    Applicant: LG Chem, Ltd.
    Inventors: Won Hee Kim, Hyo Jin Bae, Kyoung Hwan Oh, Woo Jin Cho, Jeong Heon Ahn
  • Publication number: 20150374331
    Abstract: Embodiments of the present disclosure provide an ultrasonic cavity probe including a grip configured to be held by a user, a lens unit having a predetermined curvature radius, and configured to be inserted into a bodily cavity and to be brought into contact with a skin inside the bodily cavity, a head unit including a first side for mounting the lens unit and rounded corners, and a connecting portion configured to connect the head unit and the grip and to make a first angle with the head unit.
    Type: Application
    Filed: February 7, 2013
    Publication date: December 31, 2015
    Applicants: ALPINION MEDICAL SYSTEMS CO., LTD.
    Inventors: Woo-jin CHO, Wonho NOH, Sang-woong LEE, Sang-seok LEE, Jaewon LEE, Wonse PARK
  • Publication number: 20150087500
    Abstract: The present invention relates to a neodymium compound represented by Formula 1 and a catalyst for diene polymerization including the same.
    Type: Application
    Filed: August 18, 2014
    Publication date: March 26, 2015
    Inventors: Hyo Jin BAE, Kyoung Hwan OH, Sae Young YUN, Jeong Heon AHN, Woo Jin CHO
  • Patent number: 8752572
    Abstract: A bundle trailer for containers including (i) a supporting frame on which a plurality of bundles are located; (ii) a plurality of bundles, each bundle comprising: a bundle frame, a plurality of containers containing a chemical, and at least one bundle value for controlling delivery of the chemical in the containers; (iii) at least one trailer valve; and (iv) at least one clamp for fixing the bundle is disclosed. The bundle trailer is capable of delivering high purity hygroscopic, corrosive chemicals, such as elemental fluorine and mixtures thereof, with good flexibility, high safety, and low cost.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: June 17, 2014
    Assignee: Solvay Flour GmbH
    Inventors: Michael Pittroff, Yuk-Hwan Park, Woo-Jin Cho
  • Publication number: 20110226368
    Abstract: A bundle trailer for containers including (i) a supporting frame on which a plurality of bundles are located; (ii) a plurality of bundles, each bundle comprising: a bundle frame, a plurality of containers containing a chemical, and at least one bundle value for controlling delivery of the chemical in the containers; (iii) at least one trailer valve; and (iv) at least one clamp for fixing the bundle is disclosed. The bundle trailer is capable of delivering high purity hygroscopic, corrosive chemicals, such as elemental fluorine and mixtures thereof, with good flexibility, high safety, and low cost.
    Type: Application
    Filed: October 22, 2009
    Publication date: September 22, 2011
    Applicant: SOLVAY FLUOR GMBH
    Inventors: Michael Pittroff, Yuk-Hwan Park, Woo-Jin Cho
  • Patent number: 7745290
    Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Seo, Jong-Heui Song, Jae-Seung Hwang, Min-Chul Chae, Woo-Jin Cho, Yun-Seung Kang, Young-Mi Lee
  • Publication number: 20100092875
    Abstract: An exposure mask for forming a photodiode of an image sensor and a method of manufacturing an image sensor using the exposure mask may be disclosed. An exposure mask for forming a photodiode of an image sensor includes a plurality of main open patterns, each having a first open pattern that is rectangular and a second open pattern extending outward from at least one corner of the first open pattern, and an open serif extending outward from each of the corners of the second open pattern that do not overlap with the first open pattern, covering a predetermined area adjacent to the second open pattern.
    Type: Application
    Filed: September 18, 2009
    Publication date: April 15, 2010
    Inventor: Woo Jin Cho
  • Patent number: 7531450
    Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Seung Kang, Jun Seo, Min-Chul Chae, Jae-Seung Hwang, Sung-Un Kwon, Woo-Jin Cho
  • Publication number: 20090020816
    Abstract: One embodiment generally described herein can be characterized as a semiconductor device. The semiconductor device can include a first transistor on a semiconductor substrate. A first interlayer insulating layer may be disposed over the first transistor and includes a first recess region. A single-crystalline semiconductor pattern may be disposed in the first recess region. A single-crystalline semiconductor plug may connect the semiconductor substrate to the single-crystalline semiconductor pattern. A second transistor may be disposed on the single-crystalline semiconductor pattern.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 22, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-Jin CHO, Yong-Woo LEE, Jae-Seung HWANG, Sung-Un KWON, Min-Chul CHAE
  • Publication number: 20080124871
    Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.
    Type: Application
    Filed: July 3, 2007
    Publication date: May 29, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun SEO, Jong-Heui SONG, Jae-Seung HWANG, Min-Chul CHAE, Woo-Jin CHO, Yun-Seung KANG, Young-Mi LEE