Abstract: A chamber-status monitoring apparatus includes a plurality of chambers, a time-division multiplexer configured to receive, via optical fiber probes, optical signals from each chamber, to divide each optical signal into first time slots having a predetermined duration, and to multiplex the first time slots to generate an OTDM signal, a multi-input optical emission spectroscope configured to receive and disperse the OTDM signal according to wavelengths to measure spectrum information, and a controller configured to divide the spectrum information of the dispersed OTDM signal into second time slots with a predetermined time interval therebetween, to classify the second time slots according to the chambers to obtain spectrum information of the optical signals of the individual chambers, and to control endpoint detection in each of the chambers in accordance with the spectrum information of the optical signal of the corresponding chamber.

Abstract: Disclosed herein is a method for manufacturing a light emitting diode (LED) module, the method including: disposing a circuit board at a molding space formed by an upper mold and a lower mold; adding a filling material to the molding space; hardening the filling material to form a molding cover covering at least a portion of an upper surface, a lower surface, and a side surface of the circuit board, the molding cover having an opening exposing the lower surface of the circuit board; removing the upper mold and the lower mold from the circuit board; and disposing an LED on the upper surface of the circuit board.

Abstract: A cooling system of a vehicle may include a high and low temperature radiators that cool a high and low temperature coolants respectively circulating an engine and passing a water cooled intercooler and a low exhaust gas recirculation cooler of a turbo charger, a cooling fan that blows air to the high temperature radiator and the low temperature radiator, a high temperature coolant pump that pumps the high temperature coolant, a low temperature coolant pump that pumps the low temperature coolant, and a control portion that controls the high temperature coolant pump, the low temperature coolant pump, and the cooling fan according to driving conditions of the vehicle and environmental conditions. A controlling method may include detecting driving conditions of the vehicle and environmental conditions, setting an operating target for the cooling system and/or a lubrication system, and determining operating conditions for the cooling system and/or the lubrication system.

Abstract: A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

Abstract: The present invention relates to a superconducting power transforming apparatus. The superconducting power transforming apparatus according to the present invention comprises a transformer housing having a transforming cable passing hole and filled with a liquid cooling means; a superconducting transformer housed in the transformer housing in a state that the superconducting transformer is immersed in the liquid cooling means; a tap changer housing having a tap changing cable passing hole and vacuum-sealed from outside; a power tap changer housed in the vacuum tap changer housing; and a cable linking pipe vacuum-sealed from the transformer housing and the tap changer housing, and linking the transforming cable passing hole with the tap changing passing hole in order that a transformer winding tap cable connecting the superconducting transformer and the power tap changer passes through.

Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

Abstract: A plasma processing apparatus includes a chamber for processing a substrate. A plasma generator is provided to generate plasma within the chamber. A window is provided in a sidewall of the chamber, and the window transmits light from the plasma within the chamber. A photocatalytic layer is provided on an inner surface of the window such that the photocatalytic layer is activated as a result of exposure to light from the plasma to decompose a residual product on the inner surface of the window.

Abstract: An adhesive tape for attaching and fixing electronic components has an adhesive layer on at least one surface of a heat-resistant film. The surface hardness of the adhesive layer is about more than 25 MPa, and the surface hardness of the adhesive layer is about more than 80 MPa after thermosetting at 200° C. for about one hour.

Abstract: A method for measuring critical current density of superconductor wires according to the present invention is characterized in that it includes: (a) applying an external magnetic field to the superconductor wires, (b) measuring a magnetization loss of the superconductor wires according to the application of the external magnetic field, (c) normalizing the measured magnetization loss, and then calculating a fully-penetration magnetic field of the superconductor wires according to the normalized magnetization loss, (d) calculating a critical current density of the superconductor wires according to the calculated fully-penetration magnetic field. Therefore, the critical current density of parallel superconductor wires such as stacked superconductor wires may be measured without applying current to the superconductor wires directly.

Abstract: Provided are a backlight unit and a display apparatus including the same. The display apparatus includes a display panel, a light emitting unit including a plurality of channels, each channel including light emitting diodes configured to irradiate light to the display panel, and a plurality of switches configured to enable current paths of the channels in response to switching signals, and a driver circuit configured to successively enable the switching signals corresponding to the respective channels, compare the duty ratio of the switching signals with 1/channel number, and selectively control the phases of the switching signals based on the comparison result.

Abstract: Provided is a multiple transposition method for superconducting wire, by making each superconducting wire unit from second-generation superconducting wires that were firstly transposed and then transposing each superconducting wire unit in such a manner that the phase of each unit can be changed along the length, comprising preparing wires by making curves on superconducting wires in such a manner that the superconducting wires of a thin multiple layer grown epitaxially are slit in zigzags and then making the curves repeatedly and by machining the wires with a desired length; making first-transposed superconducting wire units by combining a plurality of the prepared wires such that curves of adjacent wires come in touch to each other and are superposed; preparing a superconducting wire unit bundle by arranging the first-transposed superconducting wires units and by locating a plurality of the first-transposed superconducting wire units in parallel along the length; and making a second transposition on the fir

Abstract: The present invention relates to a superconducting power transforming apparatus. The superconducting power transforming apparatus according to the present invention comprises a transformer housing having a transforming cable passing hole and filled with a liquid cooling means; a superconducting transformer housed in the transformer housing in a state that the superconducting transformer is immersed in the liquid cooling means; a tap changer housing having a tap changing cable passing hole and vacuum-sealed from outside; a power tap changer housed in the vacuum tap changer housing; and a cable linking pipe vacuum-sealed from the transformer housing and the tap changer housing, and linking the transforming cable passing hole with the tap changing passing hole in order that a transformer winding tap cable connecting the superconducting transformer and the power tap changer passes through.

Abstract: Disclosed herein are a resin composition for no-flow underfill, which can be formed into a film, a no-flow underfill film formed from the composition and a manufacturing method of the no-flow underfill film. The resin composition for no-flow underfill has a viscosity higher than 500 cps which is suitable for coating on a film. Thus, the no-flow underfill composition can be manufactured into a laminatable film type without any additional additive. Accordingly, the resin composition makes it possible to accurately control the thickness and area of underfill, unlike the prior paste type composition.

Abstract: A noncontact method for measuring currents flowing through superconductive wires connected in parallel is provided.

Abstract: A chamber-status monitoring apparatus includes a plurality of chambers, a time-division multiplexer configured to receive, via optical fiber probes, optical signals from each chamber, to divide each optical signal into first time slots having a predetermined duration, and to multiplex the first time slots to generate an OTDM signal, a multi-input optical emission spectroscope configured to receive and disperse the OTDM signal according to wavelengths to measure spectrum information, and a controller configured to divide the spectrum information of the dispersed OTDM signal into second time slots with a predetermined time interval therebetween, to classify the second time slots according to the chambers to obtain spectrum information of the optical signals of the individual chambers, and to control endpoint detection in each of the chambers in accordance with the spectrum information of the optical signal of the corresponding chamber.

Abstract: A phase-locked loop (PLL) integrated circuit includes an oscillation control voltage generating circuit therein. The oscillation control voltage generating circuit is configured to pre-scale an output current of a charge pump therein to a first level in response to disposing the PLL integrated circuit into a pre-calibration mode of operation. The oscillation control voltage generating circuit may be responsive to an input signal (e.g., SIN) and a feedback signal (e.g., SFEED), and the magnitude of the first level of the charge pump current during the pre-calibration mode of operation may be independent of any phase difference between the input signal and the feedback signal.

Abstract: A gas supply device may include a first gas supply member that may be disposed in a chamber and around a substrate loaded in the chamber. The first gas supply member may include nozzles for providing a gas onto the substrate. A second gas supply member that may provide the gas supplied from at least one gas supply line to the first gas supply member.

Abstract: A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

Abstract: A clock multiplier includes a phase-frequency detector, a voltage-current converter, a duty ratio control circuit, a plurality of variable delay cells and an edge combiner. The phase-frequency detector generates control signals. The voltage-current converter converts the control signals to generate first and second current control voltages. The duty ratio control circuit modifies the duty ratio of an input clock signal based on the first and second current control voltages. Each of the variable delay cells generates a triangular wave voltage based on the modified input signal, generates a square wave voltage based on the triangular wave voltage to generate a delay signal. The edge combiner generates a plurality of multiplied clocks based on the delay signals from the variable delay cells.

Abstract: A clock multiplier for multiplying an input clock by N includes a phase/frequency detector, a clock selector, and a voltage-controlled delay line. The phase/frequency detector generates a first control signal and a second control signal according to a frequency/phase difference between the input clock and a count signal indicating a signal that is generated by delaying the input clock N times. The clock selector selects one of the input clock and a feedback clock based on the input clock and the count signal. The voltage-controlled delay line adjusts a delay time of the selected signal according to a control voltage that is generated based on the first control signal and the second control signal, and outputs the feedback clock based on the adjusted signal. The clock multiplier operates without accumulating a frequency/phase difference between the input clock and the output clock when the multiplying ratio is increased.