Abstract: A universal driving device includes a ring gear, a sun gear having a variable inter-axis distance with respect to a rotation shaft of the ring gear, a gear train including a series of gears configured to connect the sun gear and the ring gear, link mechanisms configured to accommodate a change in an inter-axis distance between the sun gear and the ring gear and rotatably connected with respect to each other to continuously maintain a power transmission state between the sun gear and the ring gear, a carrier configured to support a rotation shaft of a final gear engaged with the ring gear, among the gears constituting the gear train, a sun gear bearing positioned between the rotation shaft of the sun gear and each of the link mechanisms, and a sleeve positioned between the sun gear bearing and each of the link mechanisms.

Abstract: In one aspect, an electric furnace is provided with a double type melting furnace, which includes: a first upper cell that forms a first upper space of a first melting furnace in which a first iron source is introduced and molten; a second upper cell that is disposed in a horizontal direction of the first upper cell and forms a second upper space of a second melting furnace in which a second iron source is introduced and molten; a lower cell that is combined with lower portions of the first upper cell and the second upper cell and forms a single integrated space in which a first lower space of the first melting furnace and a second lower space of the second melting furnace are integrated; and a partition wall unit that is installed to vertically move up and down between the first upper cell and the second upper cell, and separates the first lower space of the first melting furnace and the second lower space of the second melting furnace, although both of the lower spaces are integrally formed by the lower cel

Abstract: A battery module includes: a battery cell assembly having a plurality of battery cells stacked therein and a plurality of frames supporting the plurality of battery cells; a front sensing assembly measuring voltages of the plurality of battery cells and mounted on a front end of the battery cell assembly; a rear sensing assembly measuring voltages of the plurality of battery cells and mounted on a rear end of the battery cell assembly; a front cover covering at least a portion of the front sensing assembly; and a rear cover covering at least a portion of the rear sensing assembly.

Abstract: A universal drive including a ring gear, a sun gear in which a sun gear axis is moveable relative to a ring gear axis of the ring gear, a gear train constituted by a series of gears configured to connect the sun gear and the ring gear to each other, a link mechanism connected to the sun gear and the ring gear in the state in which relative rotation therebetween is allowed such that a power transmission state between the sun gear and the ring gear is continuously maintained while accommodating a change in the inter-axis distance between the sun gear and the ring gear, a carrier installed so as to support a rotating shaft of a final gear engaged with the ring gear, and a sliding member located between at least one of the gears and the carrier.

Abstract: The present invention relates to a polyester nonwoven fabric with suppressed reduction in physical properties by a tufting process, a method for manufacturing same, and a backing fabric for a carpet, comprising same and, in particular, to: a polyester nonwoven fabric in which, by controlling the physical properties of fibers of a first component filament and a second filament, a reduction in physical properties is remarkably suppressed before/after a tufting process, thus enabling the manufacture of a carpet backing fabric with excellent mechanical properties; a method for manufacturing same; and a backing fabric for a carpet, manufactured thereby.

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

Abstract: A signal channel according to embodiments of the present disclosure includes a plurality of signal lines disposed on a plurality of layers spaced apart from each other in a first direction and connecting first points and second points to each other. A plurality of sections are defined between the first points and the second points. A first signal line disposed on a first layer of the plurality of layers in a first section of the plurality of sections is electrically connected to a second signal line disposed on a second layer of the plurality of layers in a second section of the plurality of sections.

Abstract: An image sensor includes a pixel array including a plurality of normal pixels, a plurality of phase detection groups, and a color filter array. Each phase detection group includes a first phase detection pixel and a second phase detection pixel disposed adjacent to the first phase detection pixel. The color filter array includes a plurality of unit groups. Each unit group includes a plurality of color filters of a same color arranged in an M×N matrix on the pixel array, wherein M and N are natural numbers. A first color filter among the color filters of a first color is disposed on the first phase detection pixel of one of the unit groups and a second color filter among the color filters of a second color different from the first color is disposed on the second phase detection pixel of another one of the unit groups.

Abstract: A semiconductor device includes a lower pattern. A channel isolation structure and a field insulating layer contact the lower pattern. A gate structure is on the lower pattern, in contact with the channel isolation structure. A channel pattern is on the lower pattern, and includes sheet patterns, each being in contact with the channel isolation structure. A source/drain pattern contacts the channel pattern and the channel isolation structure. The channel isolation structure includes a first region contacting the gate structure and a second region contacting the source/drain pattern. The second region of the channel isolation structure includes portions whose widths increase as a distance from a bottom surface of the field insulating layer increases.

Abstract: A display device includes a bank pattern disposed on a substrate, a first electrode pattern disposed on the bank pattern, a light-emitting element disposed on the first electrode pattern to be electrically connected to the first electrode pattern, a second electrode pattern configured to cover the light-emitting element, an inorganic insulating layer configured to cover the bank pattern, the first electrode pattern, and the light-emitting element between the first electrode pattern and the second electrode pattern, and a diffusion layer which includes a plurality of diffusion particles and is in contact with the inorganic insulating layer.

Abstract: A semiconductor device includes a first substrate having a first surface and a second opposite surface, a first lower interlayer insulating layer on the second surface, a first active pattern including a first lower pattern contacting the first surface, a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction, a first gate structure on the first lower pattern, a first source/drain pattern on a side of the first gate structure, a second lower interlayer insulating layer including a third surface and a fourth opposite surface, a second active pattern including a second lower pattern contacting the third surface, a plurality of second sheet patterns spaced apart from the second lower pattern in the second direction, a second gate structure on the second lower pattern, wherein the first lower pattern has a first height, and the second lower pattern has a second different height.

Abstract: A display panel and a display apparatus including the display panel are presented herein. A display panel according to one or more embodiments includes a substrate; an insulating layer on the substrate; a bank pattern on the insulating layer; a first electrode on the bank pattern; a contact electrode on the insulating layer, the contact electrode spaced apart from the bank pattern; a light-emitting element on the first electrode; a first optical layer surrounding the light-emitting element, the first optical layer comprising an organic insulating material including metal particles; a second optical layer on the contact electrode; and a third optical layer on the first optical layer.

Abstract: A gear train includes at least four gears sequentially engaged, multiple links configured to support the rotation shafts of the gears, and pins configured to fix the rotation shafts of the gears to the link, wherein the pins are installed such that, among the rotation shafts of the gears, two non-adjacent rotation shafts have both ends fixed to the link and one of adjacent rotation shafts has only one end fixed to the link.

Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

Abstract: There is provided a semiconductor device capable of improving element performance and reliability. The semiconductor device may include an active pattern that includes a lower pattern extending in a first direction on a substrate and a sheet pattern on the lower pattern, a field insulating layer that defines the active pattern on the substrate, a gate structure on the lower pattern and including a gate insulating layer and a gate electrode, the gate electrode extending in a second direction perpendicular to the first direction, a gate spacer at least partially surrounding the gate structure and including a first portion on a sidewall of the gate structure and a second portion on a bottom surface of the gate structure, and a source/drain pattern on the lower pattern and in contact with the sheet pattern.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.