Patents by Inventor WOO-SEOK PARK
WOO-SEOK PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240091730Abstract: The present invention relates to the stabilization of an effective ingredient by using a mineral material. In the present invention, the effective ingredient can be stably supported using the mineral material, and a microcapsule obtained by the manufacturing method according to the present invention, when discharged to nature, causes no environmental problems due to encapsulation ingredients thereof being the same as soil ingredients, and thus can avoid micro-plastic issues.Type: ApplicationFiled: December 28, 2021Publication date: March 21, 2024Applicants: LG HOUSEHOLD & HEALTH CARE LTD., IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)Inventors: Jun Seok YEOM, Eun Chul CHO, Ji Won LIM, Hyo Jin BONG, Seon A JEONG, No Jin PARK, Woo Sun SHIM
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Publication number: 20240086342Abstract: A semiconductor system including a transmitter configured to output a plurality of data as a plurality of data input/output signals through a plurality of channels based on a matrix E, and a receiver configured to generate the plurality of data by differentially amplifying the plurality of data input/output signals received through the plurality of channels based on a matrix D, in which all components of the matrix E and the matrix D are integers, a product matrix of the matrix D and the matrix E is a diagonal matrix, a sum of the components of each row of the matrix D is 0, and a sum of absolute values of the components of each column of the matrix D is less than or equal to a threshold value.Type: ApplicationFiled: June 27, 2023Publication date: March 14, 2024Applicants: Samsung Electronics Co., Ltd., UIF (University Industry Foundation), Yonsei UniversityInventors: HYUN JUN PARK, WOO-SEOK CHOI
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Patent number: 11908952Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.Type: GrantFiled: June 15, 2022Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Gil Yang, Woo Seok Park, Dong Chan Suh, Seung Min Song, Geum Jong Bae, Dong Il Bae
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Patent number: 11894379Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.Type: GrantFiled: June 20, 2022Date of Patent: February 6, 2024Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
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Publication number: 20230387237Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: ApplicationFiled: August 15, 2023Publication date: November 30, 2023Inventors: MYUNG GIL KANG, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Patent number: 11769813Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: GrantFiled: October 14, 2022Date of Patent: September 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Patent number: 11735629Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.Type: GrantFiled: December 3, 2021Date of Patent: August 22, 2023Inventors: Seung-Min Song, Woo-Seok Park, Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae
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Publication number: 20230238383Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.Type: ApplicationFiled: April 3, 2023Publication date: July 27, 2023Inventors: JUNG-GIL YANG, GEUM-JONG BAE, DONG-IL BAE, SEUNG-MIN SONG, WOO-SEOK PARK
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Publication number: 20230112528Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: ApplicationFiled: October 14, 2022Publication date: April 13, 2023Inventors: MYUNG GIL KANG, Dong Won KIM, Woo Seok PARK, Keun Hwi CHO, Sung Gi HUR
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Patent number: 11482606Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: GrantFiled: March 23, 2021Date of Patent: October 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
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Publication number: 20220328483Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.Type: ApplicationFiled: June 20, 2022Publication date: October 13, 2022Inventors: JUNG-GIL YANG, GEUM-JONG BAE, DONG-IL BAE, SEUNG-MIN SONG, WOO-SEOK PARK
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Publication number: 20220310852Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Inventors: Jung Gil Yang, Woo Seok PARK, Dong Chan SUH, Seung Min SONG, Geum Jong BAE, Dong Il BAE
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Patent number: 11393929Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.Type: GrantFiled: November 20, 2020Date of Patent: July 19, 2022Inventors: Jung Gil Yang, Woo Seok Park, Dong Chan Suh, Seung Min Song, Geum Jong Bae, Dong Il Bae
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Patent number: 11367723Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.Type: GrantFiled: September 30, 2020Date of Patent: June 21, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
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Publication number: 20220093735Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.Type: ApplicationFiled: December 3, 2021Publication date: March 24, 2022Inventors: Seung-Min SONG, Woo-Seok PARK, Jung-Gil YANG, Geum-Jong BAE, Dong-Il Bae
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Publication number: 20220037495Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.Type: ApplicationFiled: March 23, 2021Publication date: February 3, 2022Inventors: MYUNG GIL KANG, DONG WON KIM, WOO SEOK PARK, KEUN HWI CHO, SUNG GI HUR
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Patent number: 11222949Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.Type: GrantFiled: August 18, 2020Date of Patent: January 11, 2022Inventors: Seung-Min Song, Woo-Seok Park, Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae
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Publication number: 20210091232Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.Type: ApplicationFiled: November 20, 2020Publication date: March 25, 2021Inventors: Jung Gil Yang, Woo Seok Park, Dong Chan Suh, Seung Min Song, Geum Jong Bae, Dong Il Bae
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Patent number: 10923476Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.Type: GrantFiled: August 7, 2019Date of Patent: February 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
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Patent number: D1014265Type: GrantFiled: August 2, 2022Date of Patent: February 13, 2024Inventor: Woo Seok Park