Patents by Inventor WOO-SEOK PARK
WOO-SEOK PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11222949Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.Type: GrantFiled: August 18, 2020Date of Patent: January 11, 2022Inventors: Seung-Min Song, Woo-Seok Park, Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae
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Publication number: 20210091232Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.Type: ApplicationFiled: November 20, 2020Publication date: March 25, 2021Inventors: Jung Gil Yang, Woo Seok Park, Dong Chan Suh, Seung Min Song, Geum Jong Bae, Dong Il Bae
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Patent number: 10923476Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.Type: GrantFiled: August 7, 2019Date of Patent: February 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
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Publication number: 20210028173Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.Type: ApplicationFiled: September 30, 2020Publication date: January 28, 2021Inventors: JUNG-GIL YANG, GEUM-JONG BAE, DONG-IL BAE, SEUNG-MIN SONG, WOO-SEOK PARK
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Patent number: 10896955Abstract: A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.Type: GrantFiled: May 2, 2019Date of Patent: January 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kangmook Lim, Sang Su Kim, Woo Seok Park, Sung Gi Hur
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Patent number: 10872983Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.Type: GrantFiled: February 20, 2018Date of Patent: December 22, 2020Inventors: Jung Gil Yang, Woo Seok Park, Dong Chan Suh, Seung Min Song, Geum Jong Bae, Dong Il Bae
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Publication number: 20200381514Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: Seung-Min SONG, Woo-Seok PARK, Jung-Gil YANG, Geum-Jong BAE, Dong-Il Bae
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Patent number: 10784344Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.Type: GrantFiled: August 1, 2018Date of Patent: September 22, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Min Song, Woo-Seok Park, Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae
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Patent number: 10665723Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.Type: GrantFiled: October 16, 2018Date of Patent: May 26, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Min Song, Woo Seok Park, Geum Jong Bae, Dong Il Bae, Jung Gil Yang
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Publication number: 20200135848Abstract: A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.Type: ApplicationFiled: May 2, 2019Publication date: April 30, 2020Inventors: Kangmook Lim, Sang Su Kim, Woo Seok Park, Sung Gi Hur
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Publication number: 20190363086Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.Type: ApplicationFiled: August 7, 2019Publication date: November 28, 2019Inventors: JUNG-GIL YANG, GEUM-JONG BAE, DONG-IL BAE, SEUNG-MIN SONG, WOO-SEOK PARK
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Patent number: 10431585Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.Type: GrantFiled: December 4, 2017Date of Patent: October 1, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
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Publication number: 20190115424Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.Type: ApplicationFiled: April 27, 2018Publication date: April 18, 2019Inventors: Woo Seok PARK, Seung Min SONG, Jung Gil YANG, Geum Jong BAE, Dong Il BAE
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Publication number: 20190096996Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.Type: ApplicationFiled: August 1, 2018Publication date: March 28, 2019Inventors: Seung-Min SONG, Woo-Seok PARK, Jung-Gil YANG, Geum-Jong BAE, Dong-Il Bae
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Patent number: 10243040Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.Type: GrantFiled: April 27, 2018Date of Patent: March 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Seok Park, Seung Min Song, Jung Gil Yang, Geum Jong Bae, Dong Il Bae
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Publication number: 20190088789Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.Type: ApplicationFiled: October 16, 2018Publication date: March 21, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Min SONG, Woo Seok PARK, Geum Jong BAE, Dong Il BAE, Jung Gil YANG
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Publication number: 20190067490Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.Type: ApplicationFiled: February 20, 2018Publication date: February 28, 2019Inventors: Jung Gil Yang, Woo Seok PARK, Dong Chan SUH, Seung Min SONG, Geum Jong BAE, Dong II BAE
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Patent number: 10181510Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.Type: GrantFiled: October 6, 2017Date of Patent: January 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Gil Yang, Seung Min Song, Sung Min Kim, Woo Seok Park, Geum Jong Bae, Dong Il Bae
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Patent number: 10128379Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.Type: GrantFiled: July 12, 2017Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Min Song, Woo Seok Park, Geum Jong Bae, Dong Il Bae, Jung Gil Yang
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Publication number: 20180261668Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.Type: ApplicationFiled: October 6, 2017Publication date: September 13, 2018Inventors: JUNG GIL YANG, SEUNG MIN SONG, SUNG MIN KIM, WOO SEOK PARK, GEUM JONG BAE, DONG IL BAE