Abstract: A socket for an electrical tester is disclosed. The socket includes a first contact board being arranged at a bottom side of a test object, and a second contact board being arranged at a top side of the test object. The first contact board includes a first contact member and a first conductive connection member, wherein the first contact member is electrically connected to a bottom connection terminal formed on the bottom side of the test object, and the first conductive connection member is isolated from the test object. The second contact board includes a second contact member, wherein the second contact member is electrically connected to the first conductive connection member and a top connection terminal formed on a top side of the test object, respectively. Therefore, the socket can have a simple configuration for providing the test current.

Abstract: A remote controller device includes a transmitter; a pair of increasing and decreasing keys to increase and decrease a channel by a predetermined width; a switching key which switches the predetermined width corresponding to the pair of increasing and decreasing keys; and a controller which increases or decreases the channel by the predetermined width if the increasing key or the decreasing key is pressed, and transmits an increasing or decreasing signal to increase or decrease the channel by a wider width than the predetermined width if the increasing key or decreasing key is pressed when the switching key is selected.

Abstract: Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is serially input at a first speed and an output terminal which one-to-one corresponds to the input terminal and serially outputs the test pattern data to the outside at a second speed that is different from the first speed.

Abstract: A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal.

Abstract: A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling at least one of the impedance units from at least one of the data pads for enhanced testing of the data pads.

Abstract: Method and apparatus for use with simultaneous bi-directional (SBD) input/output circuits are included among the embodiments. In exemplary systems, the receiver in an SBD circuit compares a bit line voltage to two different voltages representing the two voltages that are expected on the bit line, based on the data that the driver in the SBD circuit is currently driving. Other embodiments are described and claimed.

Abstract: Method and apparatus for use with simultaneous bi-directional (SBD) input/output circuits are included among the embodiments. In exemplary systems, the receiver in an SBD circuit compares a bit line voltage to two different voltages representing the two voltages that are expected on the bit line, based on the data that the driver in the SBD circuit is currently driving. Other embodiments are described and claimed.

Abstract: A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to