Abstract: Disclosed are an apparatus and a method for smart energy management by controlling power consumption. Power consumption information is collected from one or more electrical device groups with a smart meter and electrical devices connected through gateways. When the method estimates that the power consumption will be larger than a threshold value, a control command is outputted to a load controller connected through the gateway and power consumption of electrical devices that belong to the electrical device using group is remotely controlled. According to an embodiment of the present invention, an energy company that produces and supplies energy can supply energy depending on a consumer's demand by using current facilities because the present invention can collect remotely energy consumption, analyze energy consumption patterns, and control automatically the energy consumption of electrical devices installed in a customer's area.

Abstract: Provided are an apparatus and method for asset tracking based on a ubiquitous sensor network (USN) using a motion sensing. The apparatus may include: a motion sensing manager to receive motion sensing information from a sensor; a filtering processor to filter the motion sensing information based on a filtering parameter and to determine whether a motion occurs based on the filtered motion sensing information; and a location information update (LU) manager to perform LU depending on whether the motion occurs.

Abstract: Provided are a method and apparatus for controlling direct memory access. In the method, data to be transmitted are read and stored in response to a direct memory access controller (DMAC) operation request, and a portion of the data corresponding to an initial burst size is first transmitted to a data destination. After resetting a burst size according to a state of the data destination, another portion of the data corresponding to the reset burst size is second-transmitted to the data destination. If all the data are not transmitted through the first-transmission and the second-transmission, the second-transmission is repeated until all the data are transmitted. If all the data are transmitted through the first-transmission and the second-transmission, an interrupt signal is generated. Therefore, interrupt signals can be less generated, and thus the processor can access an external memory less frequently, thereby increasing system performance.

Abstract: A control system, which is capable of performing a fault-tolerant function realized in the manner of duplication by merely transferring memory ownership from one processor module to another with the use of a method of extending a memory bus, is provided. Each processor module in the control system includes an A-port memory and a B-port memory which store memory data of their own processor module (the self processor module) or memory data of the other processor module and a memory bus switch which performs switching-over to selectively store data of the self processor module or data transmitted from the other processor module in the A-port or B-port memory, depending on whether the self processor module or the other processor module has memory ownership.

Abstract: A control system, which is capable of performing a fault-tolerant function realized in the manner of duplication by merely transferring memory ownership from one processor module to another with the use of a method of extending a memory bus, is provided. Each processor module in the control system includes an A-port memory and a B-port memory which store memory data of their own processor module (the self processor module) or memory data of the other processor module and a memory bus switch which performs switching-over to selectively store data of the self processor module or data transmitted from the other processor module in the A-port or B-port memory, depending on whether the self processor module or the other processor module has memory ownership.

Abstract: A concurrent write duplexing device with extension of memory bus according to the present invention includes: a primary memory having a first memory in which changed information is stored and a first memory controller for controlling the first memory; a secondary memory having a second memory in which the operating system is loaded to change an operation mode from the standby module to the active module upon failure of duplexing separation and a second memory controller for controlling the second memory; a bus transceiver part for exchanging data with a CPU through a system bus and having a bus transceiver in the first memory controller and a bus transceiver in the second memory controller, to thereby determine as to whether the first and second memory controller operate; and a memory switch part for exchanging data between the active module and the standby module and having memory switches which set direction of memory bus in accordance with an operation mode of module, so that write operation performed in t

Abstract: A high speed data transfer apparatus includes a data transfer controlling unit for outputting a signal to the standby mode system during the active mode system, and during the standby mode system, reading data and the data information stored in the second storing unit of the active mode system, storing the read contents in the second storing unit of the standby mode system, and transferring a right to a bus use through the local bus of the standby mode system, the signal being used for informing that there exists data to be transferred.