Abstract: An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

Abstract: An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

Abstract: An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

Abstract: An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

Abstract: A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount includes a base substrate having first and second surfaces, a conductive pattern on the first surface, first and second pairs of first and second electrodes on the second surface and vias extending through the base substrate between the first and second surfaces. The conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes.

Abstract: A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount includes a base substrate having first and second surfaces, a conductive pattern on the first surface, first and second pairs of first and second electrodes on the second surface and vias extending through the base substrate between the first and second surfaces. The conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes.

Abstract: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and

Abstract: Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of a second pattern to image intensity. In some methods of arranging mask patterns, a distribution of functions h(??x) is obtained which represents the contribution of a second pattern to image intensity on a first pattern. Neighboring regions of the first pattern are discretized into finite regions, and the distribution of the functions h(??x) is replaced with representative values h(x,?) of the discretized regions. A position of the second pattern is determined using polygonal regions having the same h(x,?). As described, the term x is the position of the first pattern and the term ? is the position of the assist.

Abstract: A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount including a base substrate including a first surface and a second surface different from the first surface, a conductive pattern on the first surface, a first pair and a second pair of first and second electrodes on the second surface, and vias extending through the base substrate between the first and second surfaces, wherein the conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes of the first and second pair of first and second electrodes through the vias.

Abstract: Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of a second pattern to image intensity. In some methods of arranging mask patterns, a distribution of functions h(??x) is obtained which represents the contribution of a second pattern to image intensity on a first pattern. Neighboring regions of the first pattern are discretized into finite regions, and the distribution of the functions h(??x) is replaced with representative values h(x,?) of the discretized regions. A position of the second pattern is determined using polygonal regions having the same h(x,?). As described, the term x is the position of the first pattern and the term ? is the position of the assist.

Abstract: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and

Abstract: A binary photomask with an improved resolution and a method of manufacturing the same are provided. The binary photomask may include a substrate, a transmission-prevention pattern formed on the substrate to define a circuit pattern, and a compensation layer configured to change light transmitted through the binary photomask based on a topology of the compensation layer and arranged on the transmission-prevention layer and/or the substrate.

Abstract: A sub-mount adapted for AC and DC operation of devices mountable thereon, the sub-mount including a base substrate including a first surface and a second surface different from the first surface, a conductive pattern on the first surface, a first pair and a second pair of first and second electrodes on the second surface, and vias extending through the base substrate between the first and second surfaces, wherein the conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes of the first and second pair of first and second electrodes through the vias.

Abstract: A mask for use in measuring flare produced by a projection lens of a photolithography system, a method of manufacturing the mask, a method of identifying a flare-affected region on a wafer, and a method for correcting for the flare to produce photoresist patterns of desired line widths are provided. A first photolithographic process is performed to form photoresist patterns on a test wafer using a mask including a light shielding region having a plurality of light transmission patterns and a light transmission region, and the photoresist patterns formed by light passing through the light transmission patterns of the light shielding region are compared to the photoresist patterns formed by light passing through the light transmission region. The amount of flare produced by the projection lens is quantified using the results of the comparison, and thus it is possible to identify a flare-affected region on the wafer.

Abstract: A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Abstract: A cleaning composition comprises an alkali solution, pure water, and a surfactant represented by the following chemical formula: R1-OSO3—HA+ wherein R1 is one selected from a group consisting of a butyl group, an isobutyl group, an isooctyl group, a nonyl phenyl group, an octyl phenyl group, a decyl group, a tridecyl group, a lauryl group, a myristyl group, a cetyl group, a stearyl group, an oleyl group, a licenoleyl group and a behnyl group, and A is one selected from a group consisting of ammonia, ethanol amine, diethanol amine and triethanol amine.

Abstract: A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Abstract: A binary photomask with an improved resolution and a method of manufacturing the same are provided. The binary photomask may include a substrate, a transmission-prevention pattern formed on the substrate to define a circuit pattern, and a compensation layer configured to change light transmitted through the binary photomask based on a topology of the compensation layer and arranged on the transmission-prevention layer and/or the substrate.

Abstract: A semiconductor memory device comprises a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Abstract: Provided is a method for forming a fine pattern of a semiconductor device by controlling the amount of flow of a resist pattern, including forming a resist pattern having a predetermined pattern distance on a material layer to be etched, forming a flow control barrier layer on the resist pattern to control the amount of flow during a subsequent resist flow process and to make the profile of the flowed pattern be vertical, optionally forming the flow control barrier layer by coating a material including a water-soluble high-molecular material and a crosslinking agent on the resist pattern, mixing and baking the coated material layer, and processing the resultant structure using deionized water, carrying out the flow resist process to form a hyperfine pattern and etching the lower material layer, and thereby forming fine patterns having the shape of contact holes or lines and spaces to have a critical dimension of about 100 nm or less, even with use of a KrF resist.