Patents by Inventor Woo-Sung Yang
Woo-Sung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956957Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.Type: GrantFiled: March 16, 2021Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Young Kim, Woo Sung Yang, Sung-Min Hwang, Suk Kang Sung, Joon-Sung Lim
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Publication number: 20240071907Abstract: A semiconductor device includes first and second substrates connected to each other. The second substrate includes a plate layer having first and second faces. Gate electrode layers are disposed on the first face of the plate layer. Channel structures extend through the gate electrode layers. Word-line cutting structures extend through the gate electrode layers and are spaced apart from each other. Via structures are disposed on the second face of the plate layer. Via connecting structures are disposed on the top face of the via structures. A width of the bottom face of each of the via structures is greater than a width of the top face of each of the via structures. A width of the bottom face of each of the via connecting structures is less than a width of the top face of each of the via connecting structures.Type: ApplicationFiled: May 16, 2023Publication date: February 29, 2024Inventors: Ah Reum LEE, Woo Sung YANG, Ji Mo GU, Jao Ho KIM, Suk Kang SUNG
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Patent number: 11910611Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.Type: GrantFiled: October 22, 2021Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Hoon Jang, Woo Sung Yang, Joon Sung Lim, Sung Min Hwang
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Patent number: 11456236Abstract: A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.Type: GrantFiled: December 20, 2019Date of Patent: September 27, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Sung Yang, Joon-Sung Lim, Sung-Min Hwang, Ji-Young Kim, Ji-Won Kim
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Patent number: 11446828Abstract: A parallel type integrated actuator is proposed. The actuator includes: a driving unit composed of a plurality of motors, each motor being stacked successively in a longitudinal direction of the driving unit, each motor having a stator fixed to a position outside the driving unit and a rotor positioned inside thereof, each motor rotating relative to each other; a plurality of shafts; a heat sink housing having a cylindrical shape formed around the outer surface of the driving unit, and having an inner circumferential surface thereof thermally connected with the plurality of stators and a plurality of flow paths formed on the outer circumferential surface thereof; and a blower fan installed on one end side of the driving unit, provided with a wing part disposed to be adjacent to one end side of the heat sink housing, wherein rotation generates convection for heat exchange.Type: GrantFiled: January 8, 2019Date of Patent: September 20, 2022Assignee: Ezwon Internet Service Co., Ltd.Inventors: Jae Ho Noh, Woo Sung Yang, Jin Ho Yang, Hyun Kuk Lim
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Publication number: 20220045081Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.Type: ApplicationFiled: October 22, 2021Publication date: February 10, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Dong Hoon JANG, Woo Sung YANG, Joon Sung LIM, Sung Min HWANG
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Publication number: 20220028885Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.Type: ApplicationFiled: March 16, 2021Publication date: January 27, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Young KIM, Woo Sung YANG, Sung-Min HWANG, Suk Kang SUNG, Joon-Sung LIM
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Patent number: 11201168Abstract: A semiconductor device includes a structure including gate electrodes and interlayer insulating layers alternately stacked on an upper surface of a substrate, trenches passing through the structure; and a groove passing through a portion of the structure. The gate electrodes include word lines, and first and second select lines. The word lines are stacked in a vertical direction upwardly from the upper surface of the substrate. The first and second select lines are on the word lines, and are spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate. The trenches include a first trench and a second trench spaced apart from the first trench. The groove is on the word lines. The groove and a portion of the first trench are between the first select line and the second select line. The second trench is spaced apart from the select lines.Type: GrantFiled: January 6, 2020Date of Patent: December 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Lee Eun Ku, Jae Ho Jeong, Woo Sung Yang, Jung Hwan Lee, In Su Noh, Sun Young Lee
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Patent number: 11139314Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.Type: GrantFiled: November 18, 2019Date of Patent: October 5, 2021Assignee: SAMSUNG ELECTRONIC CO., LTD.Inventors: Sung Min Hwang, Joon Sung Lim, Woo Sung Yang, Dong Sik Lee
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Patent number: 11130245Abstract: A parallel type integrated actuator is proposed. The actuator includes: a driving unit composed of a first motor, a second motor, a third motor, and a fourth motor; a first shaft, a second shaft, and a third shaft, each shaft being inserted into each other through a hollow structure and forming a co-axis, each shaft being capable of rotating relative to each other in an inserted state, and each shaft having the other end part thereof extending outside the driving unit; an distal end part disposed outside the driving unit and on which an actuator is mounted; a first link part, a second link part, and a third link part allowing the distal end part to rotate in pitching, yawing, and rolling directions; and a universal link part connecting the fourth rotor, which is a rotor of the fourth motor, and the distal end part to each other.Type: GrantFiled: January 8, 2019Date of Patent: September 28, 2021Assignee: Ezwon Tnternet Service Co., Ltd.Inventors: Jae Ho Noh, Jae Yong Lee, Dae Je Kim, Jae Sung Kwon, Woo Sung Yang, Jin Ho Yang, Hyun Kuk Lim
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Publication number: 20200384656Abstract: A parallel type integrated actuator is proposed. The actuator includes: a driving unit composed of a first motor, a second motor, a third motor, and a fourth motor; a first shaft, a second shaft, and a third shaft, each shaft being inserted into each other through a hollow structure and forming a co-axis, each shaft being capable of rotating relative to each other in an inserted state, and each shaft having the other end part thereof extending outside the driving unit; an distal end part disposed outside the driving unit and on which an actuator is mounted; a first link part, a second link part, and a third link part allowing the distal end part to rotate in pitching, yawing, and rolling directions; and a universal link part connecting the fourth rotor, which is a rotor of the fourth motor, and the distal end part to each other.Type: ApplicationFiled: January 8, 2019Publication date: December 10, 2020Inventors: Jae Ho Noh, Jae Yong Lee, Dae Je Kim, Jae Sung Kwon, Woo Sung Yang, Jin Ho Yang, Hyun Kuk Lim
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Publication number: 20200376687Abstract: A parallel type integrated actuator is proposed. The actuator includes: a driving unit composed of a plurality of motors, each motor being stacked successively in a longitudinal direction of the driving unit, each motor having a stator fixed to a position outside the driving unit and a rotor positioned inside thereof, each motor rotating relative to each other; a plurality of shafts; a heat sink housing having a cylindrical shape formed around the outer surface of the driving unit, and having an inner circumferential surface thereof thermally connected with the plurality of stators and a plurality of flow paths formed on the outer circumferential surface thereof; and a blower fan installed on one end side of the driving unit, provided with a wing part disposed to be adjacent to one end side of the heat sink housing, wherein rotation generates convection for heat exchange.Type: ApplicationFiled: January 8, 2019Publication date: December 3, 2020Inventors: Jae Ho NOH, Woo Sung YANG, Jin Ho YANG, Hyun Kuk LIM
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Publication number: 20200303284Abstract: A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.Type: ApplicationFiled: December 20, 2019Publication date: September 24, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Woo-Sung YANG, Joon-Sung LIM, Sung-Min HWANG, Ji-Young KIM, Ji-Won KIM
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Publication number: 20200227435Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.Type: ApplicationFiled: November 18, 2019Publication date: July 16, 2020Inventors: Sung Min Hwang, Joon Sung Lim, Woo Sung Yang, Dong Sik Lee
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Publication number: 20200176464Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.Type: ApplicationFiled: July 16, 2019Publication date: June 4, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dong Hoon Jang, Woo Sung YANG, Joon Sung LIM, Sung Min HWANG
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Publication number: 20200144290Abstract: A semiconductor device includes a structure including gate electrodes and interlayer insulating layers alternately stacked on an upper surface of a substrate, trenches passing through the structure; and a groove passing through a portion of the structure. The gate electrodes include word lines, and first and second select lines. The word lines are stacked in a vertical direction upwardly from the upper surface of the substrate. The first and second select lines are on the word lines, and are spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate. The trenches include a first trench and a second trench spaced apart from the first trench. The groove is on the word lines. The groove and a portion of the first trench are between the first select line and the second select line. The second trench is spaced apart from the select lines.Type: ApplicationFiled: January 6, 2020Publication date: May 7, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Lee Eun Ku, Jae Ho Jeong, Woo Sung Yang, Jung Hwan Lee, In Su Noh, Sun Young Lee
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Patent number: 10546876Abstract: Semiconductor devices are provided. A semiconductor device includes first and second stacks of electrodes. Moreover, the semiconductor device includes first and second connection lines that connect the first and second stacks of electrodes. In some embodiments, the first connection lines have a first length and the second connection lines have a second length that is longer than the first length of the first connection lines. In some embodiments, the first connection lines connect inner portions of the first stack of electrodes to inner portions of the second stack of electrodes. In some embodiments, the second connection lines connect outer portions of the first stack of electrodes to outer portions of the second stack of electrodes.Type: GrantFiled: June 28, 2018Date of Patent: January 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Min Lee, Woo-Sung Yang, Kwan-Yong Kim
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Patent number: 10529734Abstract: A semiconductor device can include a semiconductor substrate having a memory cell region and a pad region that is adjacent to the memory cell region, the pad region can include a first pad region, a second pad region between the memory cell region and the first pad region, and a buffer region that is between the first and second pad regions. A separation source structure can include a first portion and a second portion that are parallel to each other in a plan view of the semiconductor device. A first source structure and a second source structure can be disposed between the first and second portions of the separation source structure, where the first and second source structures can have end portions that oppose each other, the first source structure being disposed in the first pad region, and the second source structure being disposed in the second pad region.Type: GrantFiled: January 12, 2018Date of Patent: January 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Lee Eun Ku, Jae Ho Jeong, Woo Sung Yang, Jung Hwan Lee, In Su Noh, Sun Young Lee
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Patent number: 10283451Abstract: A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.Type: GrantFiled: November 13, 2017Date of Patent: May 7, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-hoon Kim, Woo-sung Yang, Jee-hoon Hwang
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Publication number: 20180358375Abstract: A semiconductor device can include a semiconductor substrate having a memory cell region and a pad region that is adjacent to the memory cell region, the pad region can include a first pad region, a second pad region between the memory cell region and the first pad region, and a buffer region that is between the first and second pad regions. A separation source structure can include a first portion and a second portion that are parallel to each other in a plan view of the semiconductor device. A first source structure and a second source structure can be disposed between the first and second portions of the separation source structure, where the first and second source structures can have end portions that oppose each other, the first source structure being disposed in the first pad region, and the second source structure being disposed in the second pad region.Type: ApplicationFiled: January 12, 2018Publication date: December 13, 2018Inventors: LEE EUN KU, JAE HO JEONG, WOO SUNG YANG, JUNG HWAN LEE, IN SU NOH, SUN YOUNG LEE