Abstract: A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

Abstract: Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

Abstract: Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

Abstract: In a phase change random access memory (PRAM) device, data is programmed in selected memory cells using a plurality of program loops. In each program loop, division program operations for cell groups including the selected memory cells are performed in consecutive timeslots.

Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Abstract: In various methods of performing program operations in phase change memory devices, selected memory cells are repeatedly programmed to obtain resistance distributions having desired characteristics such as adequate sensing margins.

Abstract: A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write driver circuit comprises a set current driver and a reset current driver. The set current driver is adapted to provide a set current to a selected memory cell among the plurality of memory cells and the reset current driver is adapted to provide a reset current to a selected memory cell among the plurality of memory cells.

Abstract: An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

Abstract: A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.

Abstract: An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method includes providing a memory cell array having first through third nonvolatile memory cells where each memory cell is capable of storing one among first data through third data corresponding to first through third resistance levels, respectively. Each of the resistance levels is different from one another. First and the third data are written to the first and third nonvolatile memory cells, respectively, during a first interval of a write operation. Second data is written to the second nonvolatile memory cell during a second interval of the write operation.

Abstract: A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.

Abstract: A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.

Abstract: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of p

Abstract: A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.

Abstract: A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.

Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1.