Abstract: A method for fabricating a semiconductor device includes forming a target etch layer over a substrate, a first auxiliary layer over the target etch layer, an isolation layer over the first auxiliary layer, and a second auxiliary layer over the isolation layer. A first exposure process is performed, where the first auxiliary layer is in focus and the second auxiliary layer is out of focus. A second exposure process is performed, where the second auxiliary layer in focus and the first auxiliary layer is out of focus. The second auxiliary layer is developed to form first mask patterns. The isolation layer and the first auxiliary layer are etched by using the first mask patterns to form second mask patterns. The second mask patterns are developed to form third mask patterns that are used to facilitate subsequent etching of the target etch layer.

Abstract: The present invention relates to a method of forming a micro pattern of a semiconductor device. In the method according to an aspect of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern.

Abstract: In a method of forming hard mask patterns in a semiconductor device, an etch mask has a pitch less than a resolution limitation of exposure equipment. The method includes forming first hard mask patterns through an exposure process utilizing photoresist patterns, forming a separation layer on a resulting structure including the first hard mask patterns, forming a second hard mask pattern in a space between the first hard mask patterns, and removing the exposed separation layer.

Abstract: The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for a hard mask. Spacers are formed on top surfaces and sidewalls of the plurality of first hard mask patterns. A second hard mask film is formed over a total surface including the spacers. Second hard mask patterns are formed in spaces between the spacers by performing an etch process so that a top surface of the spacers is exposed. The spacers are removed. Accordingly, gate patterns can be formed by employing hard mask patterns having a pitch of exposure equipment resolutions or less.

Abstract: A method of forming a micro pattern in a semiconductor device includes forming an etching object layer and a hard mask layer on a semiconductor substrate. Cross-shaped first auxiliary patterns are formed on the hard mask layer. An insulating layer is formed on the hard mask layer including the first auxiliary pattern. A second auxiliary pattern is formed on the insulating layer between the first auxiliary patterns. An etching process is performed such that the insulating layer remains only on a lower portion of the second auxiliary pattern. The hard mask is etched through an etching process using the first and second auxiliary patterns as an etching mask to form a hard mask pattern. The etching object layer is etched using the hard mask pattern as an etching mask.

Abstract: A method of forming a micro pattern of a semiconductor device method includes forming an etch target layer over a substrate, a hard mask layer over the etch target layer, and first auxiliary patterns over the etch target layer. The first auxiliary patterns defining a plurality of structures that are spaced apart from each other. Silicon is injected into the first auxiliary patterns to form silylated first auxiliary patterns. An insulating layer is formed over the hard mask layer and the silylated first auxiliary patterns, the insulating layer defining a space between two adjacent silylated first auxiliary patterns. A second auxiliary pattern is formed over the insulating layer at the space defined between the two silylated first auxiliary patterns. The insulating layer is etched to remove a portion of the insulating layer provided between the silylated first auxiliary patterns and the second auxiliary pattern while not removing a portion of the insulating layer provided below the second auxiliary pattern.

Abstract: A method of forming a micro pattern of a semiconductor device includes forming an etch target layer, a hard mask layer, a Bottom Anti-Reflective Coating (BARC) layer and a first photoresist pattern over a semiconductor substrate. An organic layer is formed on a surface of the first photoresist pattern. A second photoresist layer is formed over the BARC layer and the organic layer. An etch process is performed so that the second photoresist layer remains on the BARC layer between the first photoresist patterns and becomes a second photoresist pattern. The organic layer on the first photoresist pattern and between the first and second photoresist patterns is removed. The BARC layer formed below the organic layer is removed. The hard mask layer is etched using the first and second photoresist patterns as an etch mask. The etch target layer is etched using a hard mask pattern as an etch mask.

Abstract: A method of forming a fine pattern in a semiconductor device includes forming an target layer, a hard mask layer and first sacrificial patterns on a semiconductor substrate; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; performing the first etch process so as to allow the second sacrificial layer remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns; removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns; etch the hard mask layer through the second etch process utilizing the first and second sacrificial patterns as the etch mask to form a mask pattern; and etch the target layer through the third etch process utilizing the hard mask pattern as the etch mask.

Abstract: A method of forming a contact hole of a semiconductor device is disclosed. At the time of a hard mask formation process for forming a contact hole of a semiconductor device, first patterns are formed using a photoresist pattern employing an exposure process. Spacers having a predetermined thickness are formed on sidewalls of the first patterns using an amorphous carbon layer. Spaces between the first patterns including the spacers are gap filled to form second patterns. Accordingly, a contact hole having a pitch with exposure equipment resolution or less can be formed.

Abstract: A method of forming a hardmask pattern over a semiconductor device semiconductor device includes forming a first hardmask layer over a semiconductor substrate. First and second structures are formed over the first hardmask layer, the first and second structures formed of the same material, the first and second structures defining a first pitch. First and second overcoats are formed over the first and second structures, respectively, the first and second overcoats being conformal to the first and second structures, respectively. The first and second overcoats define a space therebetween and are configured to expose an underlying layer. A filling layer is formed to fill the space defined between the first and second overcoats. The first and second overcoats are removed to provide the first structure, the second structure, and a third structure provided between the first and second structures, the first and third structures defining a second pitch, the second and third structures defining a third pitch.

Abstract: A method of forming a pattern of a semiconductor device includes forming a hard mask layer over a semiconductor substrate and forming a photoresist film pattern over the hard mask layer. An outer portion of the photoresist film pattern is converted into an oxide layer having a first vertical wall, a second vertical wall, and a horizontal wall, wherein an inner portion of the photoresist film pattern is enclosed within the converted oxide layer. At least a portion of the horizontal wall is removed to expose the photoresist film pattern remaining within the converted oxide layer. The exposed photoresist film pattern is removed to form first and second oxide patterns corresponding to the first and second vertical walls, respectively, of the oxide layer. The hard mask layer is patterned using the first and second oxide patterns as etch masks. The semiconductor substrate is etched using the patterned hard mask layer.

Abstract: A method of forming a hardmask pattern over a semiconductor device semiconductor device includes forming a first hardmask layer over a semiconductor substrate. First and second structures are formed over the first hardmask layer, the first and second structures formed of the same material, the first and second structures defining a first pitch. First and second overcoats are formed over the first and second structures, respectively, the first and second overcoats being conformal to the first and second structures, respectively. The first and second overcoats define a space therebetween and are configured to expose an underlying layer. A filling layer is formed to fill the space defined between the first and second overcoats. The first and second overcoats are removed to provide the first structure, the second structure, and a third structure provided between the first and second structures, the first and third structures defining a second pitch, the second and third structures defining a third pitch.

Abstract: A method of manufacturing a flash memory device, including the steps of forming a gate on a semiconductor substrate in which a cell region, a source selection line region, and a drain selection line region are defined and then forming spacers on sidewalls of the gate; depositing a nitride film and a first interlayer insulating film on the entire structure, etching a region of the first interlayer insulating film to form a source contact hole, forming a conductive film on the entire structure to bury the source contact hole, and polishing the conductive film; forming a second interlayer insulating film on the entire structure, and then etching the second and first interlayer insulating films and the nitride film using a mask through which regions in which a cell region and a drain contact will be formed are opened; and, forming a polysilicon layer on the entire structure.

Abstract: A method of manufacturing a flash memory device includes providing a substrate having an insulating layer, a first mask layer over the insulating layer, a second mask layer over the first mask layer, a first photoresist pattern over the second mask layer, the first photoresist pattern having a first pitch. A material layer is provided over the first photoresist pattern. The material layer is etched to convert the material layer into a material layer pattern having a second pitch that is less than the first pitch. The second hard mask layer is etched using the material layer pattern to form a second hard mask layer pattern that extends along a first direction. A second photoresist pattern is etched, the second photoresist pattern defining a first region that is not exposed and a second region that is exposed, the second region extending along a second direction that is orthogonal to the first direction.

Abstract: A method for manufacturing a semiconductor device, in forming plugs, an alignment error margin between wirings and lower plugs is increased by using a conductive pad and thus avoids an increase of a contact resistance caused by an alignment error and improves reliability.

Abstract: A method of manufacturing a flash memory device, including the steps of forming a gate on a semiconductor substrate in which a cell region, a source selection line region, and a drain selection line region are defined and then forming spacers on sidewalls of the gate; depositing a nitride film and a first interlayer insulating film on the entire structure, etching a region of the first interlayer insulating film to form a source contact hole, forming a conductive film on the entire structure to bury the source contact hole, and polishing the conductive film; forming a second interlayer insulating film on the entire structure, and then etching the second and first interlayer insulating films and the nitride film using a mask through which regions in which a cell region and a drain contact will be formed are opened; and, forming a polysilicon layer on the entire structure.

Abstract: A method for forming a semiconductor device includes forming a plurality of drain contact holes in a first interlayer insulating layer provided over a semiconductor substrate. First metal material having a predetermined thickness is formed over the first interlayer insulating layer, the first metal material filling the drain contact holes. A first metal layer is formed by patterning the first metal material, the first metal layer having a plurality of lines of a first type and a plurality of landing pads. A second interlayer insulating layer is formed over the patterned first metal material. A plurality of trenches is formed in the second interlayer insulating layer, the trenches exposing the landing pads. A second metal layer is formed by providing second metal material over the second interlayer insulating layer and filling the trenches, the second metal layer including a plurality of lines of a second type defined within the trenches, the lines of the second type contacting the landing pads.

Abstract: A half-tone phase shift mask capable of preventing light from being transmitted in undesired areas, and thus capable of obtaining desired fine patterns. The present invention is to provide a photomask for simultaneously forming photoresist patterns on a first area in which fine patterns are to be formed and on a second area in which relatively large photoresist patterns are to be formed in a semiconductor device. The photomask comprises a transparent substrate, half-tone phase shift patterns disposed on the first area of the transparent substrate and light screen patterns disposed on the second area of the transparent substrate.