Patents by Inventor Wook-Ghee Hahn
Wook-Ghee Hahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230223088Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.Type: ApplicationFiled: March 19, 2023Publication date: July 13, 2023Inventors: YOUN-YEOL LEE, WOOK-GHEE HAHN
-
Patent number: 11631465Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.Type: GrantFiled: October 6, 2021Date of Patent: April 18, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
-
Publication number: 20220028461Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Inventors: YOUN-YEOL LEE, WOOK-GHEE HAHN
-
Patent number: 11164638Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.Type: GrantFiled: September 8, 2020Date of Patent: November 2, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
-
Patent number: 10998052Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.Type: GrantFiled: August 18, 2020Date of Patent: May 4, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
-
Publication number: 20200411108Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.Type: ApplicationFiled: September 8, 2020Publication date: December 31, 2020Inventors: YOUN-YEOL LEE, WOOK-GHEE HAHN
-
Publication number: 20200381059Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: YOUN-YEOL LEE, WOOK-GHEE HAHN
-
Patent number: 10790291Abstract: A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.Type: GrantFiled: January 7, 2019Date of Patent: September 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
-
Patent number: 10770150Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.Type: GrantFiled: November 5, 2018Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
-
Publication number: 20200013787Abstract: A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.Type: ApplicationFiled: January 7, 2019Publication date: January 9, 2020Inventors: YOUN-YEOL LEE, WOOK-GHEE HAHN
-
Publication number: 20190318787Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.Type: ApplicationFiled: November 5, 2018Publication date: October 17, 2019Inventors: YOUN-YEOL LEE, WOOK-GHEE HAHN
-
Patent number: 10090045Abstract: Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device includes: programming a first set of memory cells of the plurality of memory cells to a target state based on a primary program voltage such that a threshold voltage distribution of the first set of memory cells is formed; grouping the first set of memory cells into a plurality of cell groups at least one cell group having a different threshold voltage distribution width from others, based on program speeds of the first set of memory cells; and reprogramming remaining cell groups other than a first cell group that is programmed to the target state among the plurality of cell groups, to the target state based on a plurality of secondary program voltages determined based on threshold voltage distribution widths of the plurality of cell groups.Type: GrantFiled: March 11, 2018Date of Patent: October 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wook-ghee Hahn, Chang-yeon Yu, Joo-kwang Lee
-
Patent number: 10056152Abstract: In a method of reading data in a nonvolatile memory device including a plurality of memory cells arranged at intersections of a plurality of word-lines and a plurality of bit-lines, a read request on a first word-line of the plurality of word-lines is received, a read operation is performed on a second word-line adjacent to the first word-line and a read operation is performed on the first word-line based on data read from memory cells of the second word-line. The read operation on the first word-line is performed by adjusting a level of recover read voltage applied to the first word-line during the read operation of the first word-line based on at least one of a program state of the data read from memory cells of the second word-line and an operating parameter of the nonvolatile memory device.Type: GrantFiled: April 21, 2017Date of Patent: August 21, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wook-Ghee Hahn, Ji-Sang Lee
-
Publication number: 20180204614Abstract: Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device includes: programming a first set of memory cells of the plurality of memory cells to a target state based on a primary program voltage such that a threshold voltage distribution of the first set of memory cells is formed; grouping the first set of memory cells into a plurality of cell groups at least one cell group having a different threshold voltage distribution width from others, based on program speeds of the first set of memory cells; and reprogramming remaining cell groups other than a first cell group that is programmed to the target state among the plurality of cell groups, to the target state based on a plurality of secondary program voltages determined based on threshold voltage distribution widths of the plurality of cell groups.Type: ApplicationFiled: March 11, 2018Publication date: July 19, 2018Inventors: Wook-ghee HAHN, Chang-yeon YU, Joo-kwang LEE
-
Patent number: 9953703Abstract: Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device includes: programming a first set of memory cells of the plurality of memory cells to a target state based on a primary program voltage such that a threshold voltage distribution of the first set of memory cells is formed; grouping the first set of memory cells into a plurality of cell groups at least one cell group having a different threshold voltage distribution width from others, based on program speeds of the first set of memory cells; and reprogramming remaining cell groups other than a first cell group that is programmed to the target state among the plurality of cell groups, to the target state based on a plurality of secondary program voltages determined based on threshold voltage distribution widths of the plurality of cell groups.Type: GrantFiled: October 17, 2016Date of Patent: April 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wook-ghee Hahn, Chang-yeon Yu, Joo-kwang Lee
-
Publication number: 20180090216Abstract: In a method of reading data in a nonvolatile memory device including a plurality of memory cells arranged at intersections of a plurality of word-lines and a plurality of bit-lines, a read request on a first word-line of the plurality of word-lines is received, a read operation is performed on a second word-line adjacent to the first word-line and a read operation is performed on the first word-line based on data read from memory cells of the second word-line. The read operation on the first word-line is performed by adjusting a level of recover read voltage applied to the first word-line during the read operation of the first word-line based on at least one of a program state of the data read from memory cells of the second word-line and an operating parameter of the nonvolatile memory device.Type: ApplicationFiled: April 21, 2017Publication date: March 29, 2018Inventors: Wook-Ghee HAHN, Ji-Sang LEE
-
Patent number: 9818483Abstract: A row decoder of the semiconductor memory device includes a decoding and precharging unit that is connected between a high voltage node and a block word line, wherein the decoding and precharging unit precharges the block word line, and wherein the decoding and precharging unit includes one or more decoding transistors that decode an address and form a transmission path for transmitting a block selection voltage. The row decoder further includes a pass transistor block that transmits one or more row driving voltages to row lines in response to the block selection voltage, wherein the block selection voltage is boosted according to a switching operation of the pass transistor block.Type: GrantFiled: September 13, 2016Date of Patent: November 14, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wook-Ghee Hahn, Chang-Yeon Yu
-
Publication number: 20170110185Abstract: Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device includes: programming a first set of memory cells of the plurality of memory cells to a target state based on a primary program voltage such that a threshold voltage distribution of the first set of memory cells is formed; grouping the first set of memory cells into a plurality of cell groups at least one cell group having a different threshold voltage distribution width from others, based on program speeds of the first set of memory cells; and reprogramming remaining cell groups other than a first cell group that is programmed to the target state among the plurality of cell groups, to the target state based on a plurality of secondary program voltages determined based on threshold voltage distribution widths of the plurality of cell groups.Type: ApplicationFiled: October 17, 2016Publication date: April 20, 2017Inventors: Wook-ghee HAHN, Chang-yeon YU, Joo-kwang LEE
-
Publication number: 20170084335Abstract: A row decoder of the semiconductor memory device includes a decoding and precharging unit that is connected between a high voltage node and a block word line, wherein the decoding and precharging unit precharges the block word line, and wherein the decoding and precharging unit includes one or more decoding transistors that decode an address and form a transmission path for transmitting a block selection voltage. The row decoder further includes a pass transistor block that transmits one or more row driving voltages to row lines in response to the block selection voltage, wherein the block selection voltage is boosted according to a switching operation of the pass transistor block.Type: ApplicationFiled: September 13, 2016Publication date: March 23, 2017Inventors: Wook-Ghee HAHN, Chang-Yeon YU
-
Patent number: 9378837Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.Type: GrantFiled: July 21, 2015Date of Patent: June 28, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moo Sung Kim, Wook Ghee Hahn