Patents by Inventor Wookyung You
Wookyung You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10875091Abstract: A method for manufacturing metal powder is provided. The method includes preparing first metal powder, agglomerating the first metal powder to manufacture second metal powder in which the first metal powder is agglomerated, coating the second metal powder with an organic binder, and agglomerating and coarsening the second metal powder coated with the organic binder to manufacture third metal powder having higher flowability than the second metal powder coated with the organic binder.Type: GrantFiled: April 1, 2015Date of Patent: December 29, 2020Assignees: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION, HANYANG UNIVERSITY ERICA CAMPUSInventors: Jaisung Lee, Wookyung You
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Patent number: 10707164Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.Type: GrantFiled: March 8, 2019Date of Patent: July 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
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Patent number: 10497647Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.Type: GrantFiled: November 17, 2017Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jongmin Baek, Sangho Rha, Sanghoon Ahn, Wookyung You, Naein Lee
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Publication number: 20190206794Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangho RHA, Jongmin BAEK, Wookyung YOU, Sanghoon AHN, Nae-In LEE
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Patent number: 10269712Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.Type: GrantFiled: March 21, 2018Date of Patent: April 23, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
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Patent number: 10192782Abstract: A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.Type: GrantFiled: June 23, 2015Date of Patent: January 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woojin Lee, VietHa Nguyen, Wookyung You, Doo-Sung Yun, Hyunbae Lee, Byunghee Kim, Sang Hoon Ahn, Seungyong Yoo, Naein Lee, Hoyun Jeon
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Patent number: 10186485Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.Type: GrantFiled: February 15, 2018Date of Patent: January 22, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
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Patent number: 10141258Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.Type: GrantFiled: July 25, 2017Date of Patent: November 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Naein Lee
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Patent number: 10090381Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.Type: GrantFiled: June 21, 2017Date of Patent: October 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongmin Baek, Vietha Nguyen, Wookyung You, Sangshin Jang, Byunghee Kim, Kyu-Hee Han
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Publication number: 20180218980Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.Type: ApplicationFiled: March 21, 2018Publication date: August 2, 2018Inventors: Sangho Rha, Jongmin Beak, Wookyung You, Sanghoon Ahn, Nae-In Lee
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Publication number: 20180174977Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
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Patent number: 9972528Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.Type: GrantFiled: December 9, 2016Date of Patent: May 15, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: VietHa Nguyen, Thomas Oszinda, Jongmin Baek, Sanghoon Ahn, Byunghee Kim, Wookyung You, Naein Lee
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Patent number: 9953924Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.Type: GrantFiled: June 9, 2017Date of Patent: April 24, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
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Patent number: 9929099Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.Type: GrantFiled: November 21, 2016Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
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Publication number: 20180083099Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.Type: ApplicationFiled: June 21, 2017Publication date: March 22, 2018Inventors: JONGMIN BAEK, VIETHA NGUYEN, WOOKYUNG YOU, Sangshin JANG, BYUNGHEE KIM, Kyu-Hee HAN
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Publication number: 20180076127Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.Type: ApplicationFiled: November 17, 2017Publication date: March 15, 2018Inventors: Jongmin Baek, Sangho Rha, Sanghoon Ahn, Wookyung You, Naein Lee
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Patent number: 9911644Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.Type: GrantFiled: November 23, 2016Date of Patent: March 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wookyung You, Jongmin Baek, Sanghoon Ahn, Sangho Rha, Naein Lee
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Patent number: 9842803Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.Type: GrantFiled: December 12, 2016Date of Patent: December 12, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jongmin Baek, Sangho Rha, Sanghoon Ahn, Wookyung You, Naein Lee
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Publication number: 20170326641Abstract: A method for manufacturing metal powder is provided. The method includes preparing first metal powder, agglomerating the first metal powder to manufacture second metal powder in which the first metal powder is agglomerated, coating the second metal powder with an organic binder, and agglomerating and coarsening the second metal powder coated with the organic binder to manufacture third metal powder having higher flowability than the second metal powder coated with the organic binder.Type: ApplicationFiled: April 1, 2015Publication date: November 16, 2017Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUSInventors: Jaisung Lee, Wookyung You
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Publication number: 20170323850Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.Type: ApplicationFiled: July 25, 2017Publication date: November 9, 2017Inventors: SANGHO RHA, JONGMIN BAEK, WOOKYUNG YOU, SANGHOON AHN, NAEIN LEE