Patents by Inventor Wookyung You

Wookyung You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9799606
    Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hoon Ahn, Sangho Rha, Jongmin Baek, Wookyung You, Nae-In Lee
  • Publication number: 20170278797
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: SANGHO RHA, JONGMIN BAEK, WOOKYUNG YOU, SANGHOON AHN, NAE-IN LEE
  • Patent number: 9748170
    Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 29, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Naein Lee
  • Patent number: 9711453
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Publication number: 20170178949
    Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 22, 2017
    Inventors: VietHa Nguyen, Thomas Oszinda, Jongmin Baek, Sanghoon Ahn, Byunghee Kim, Wookyung You, Naein Lee
  • Publication number: 20170170184
    Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
    Type: Application
    Filed: November 21, 2016
    Publication date: June 15, 2017
    Inventors: VietHa Nguyen, Wookyung You, Inoue Naoya, Hak-Sun Lee, Byung-Kwon Cho, Songyi Han, Jongmin Baek, Jiwon Kang, Byunghee Kim, Young-Ju Park, Sanghoon Ahn, Jiwon Yun, Naein Lee, YoungWoo Cho
  • Publication number: 20170092578
    Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Inventors: Jongmin BAEK, Sangho RHA, Sanghoon AHN, Wookyung YOU, Naein LEE
  • Publication number: 20170076975
    Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.
    Type: Application
    Filed: November 23, 2016
    Publication date: March 16, 2017
    Inventors: WOOKYUNG YOU, JONGMIN BAEK, SANGHOON AHN, SANGHO RHA, NAEIN LEE
  • Patent number: 9558994
    Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wookyung You, Sanghoon Ahn, Sangho Rha, Jongmin Baek, Nae-In Lee
  • Patent number: 9524937
    Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: December 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongmin Baek, Sangho Rha, Sanghoon Ahn, Wookyung You, Naein Lee
  • Patent number: 9520300
    Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: December 13, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wookyung You, Jongmin Baek, Sanghoon Ahn, Sangho Rha, Naein Lee
  • Publication number: 20160322254
    Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.
    Type: Application
    Filed: July 8, 2016
    Publication date: November 3, 2016
    Inventors: WOOKYUNG YOU, Sanghoon Ahn, Sangho Rha, Jongmin Baek, Nae-In Lee
  • Publication number: 20160293547
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Application
    Filed: May 16, 2016
    Publication date: October 6, 2016
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Publication number: 20160247759
    Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: SANGHO RHA, JONGMIN BAEK, WOOKYUNG YOU, SANGHOON AHN, NAEIN LEE
  • Patent number: 9406553
    Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: August 2, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wookyung You, Sanghoon Ahn, Sangho Rha, Jongmin Baek, Nae-In Lee
  • Patent number: 9368362
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: June 14, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Patent number: 9343409
    Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Naein Lee
  • Publication number: 20160133512
    Abstract: A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.
    Type: Application
    Filed: June 23, 2015
    Publication date: May 12, 2016
    Inventors: Woojin LEE, VietHa NGUYEN, Wookyung YOU, Doo-Sung YUN, Hyunbae LEE, Byunghee KIM, Sang Hoon AHN, Seungyong YOO, Naein LEE, Hoyun JEON
  • Publication number: 20150332955
    Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.
    Type: Application
    Filed: January 27, 2015
    Publication date: November 19, 2015
    Inventors: WOOKYUNG YOU, JONGMIN BAEK, SANGHOON AHN, SANGHO RHA, NAEIN LEE
  • Publication number: 20150287682
    Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.
    Type: Application
    Filed: March 4, 2015
    Publication date: October 8, 2015
    Inventors: Sang Hoon AHN, Sangho RHA, Jongmin BAEK, Wookyung YOU, Nae-In LEE