Patents by Inventor Woon-Kyung Lee

Woon-Kyung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190378854
    Abstract: A method of manufacturing a semiconductor device includes forming a preliminary stacked structure by alternately stacking mold insulating layers and preliminary sacrificial layers on a substrate, forming channel holes passing through the preliminary stacked structure, and converting the preliminary sacrificial layers into sacrificial layers through the channel holes, and the sacrificial layers have thicknesses greater than thicknesses of the preliminary sacrificial layers.
    Type: Application
    Filed: December 12, 2018
    Publication date: December 12, 2019
    Inventors: WOON KYUNG LEE, YOUN JOUNG CHO
  • Patent number: 10461030
    Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: October 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Young-Ho Lee, Seong-Soon Cho, Woon-Kyung Lee
  • Publication number: 20170040254
    Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min HWANG, Young-Ho LEE, Seong-Soon CHO, Woon-Kyung LEE
  • Patent number: 9306041
    Abstract: A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: April 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Woon-Kyung Lee, Won-Seok Cho
  • Patent number: 9305830
    Abstract: A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n?1 first recesses penetrating 20 through 2n?1 deposited sacrificial layers and forming a buried insulating layer group including 2n?1 buried insulating layers filling the 2n?1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n?1 buried insulating layers may be formed.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yong Park, Woon-kyung Lee, Jin-taek Park
  • Patent number: 9299716
    Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: March 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Woon-Kyung Lee, Won-Seok Cho
  • Publication number: 20150357346
    Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.
    Type: Application
    Filed: August 20, 2015
    Publication date: December 10, 2015
    Inventors: BYONG-HYUN JANG, JUHYUNG KIM, WOON KYUNG LEE, JAEGOO LEE, CHAEHO KIM, JUNKYU YANG, PHIL OUK NAM, JAEYOUNG AHN, KlHYUN HWANG
  • Patent number: 9209244
    Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joo Shim, Han-Soo Kim, Woon-Kyung Lee, Ju-Young Lim, Sung-Min Hwang
  • Publication number: 20150311213
    Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.
    Type: Application
    Filed: July 2, 2015
    Publication date: October 29, 2015
    Inventors: Sung-Min HWANG, Han-Soo KIM, Woon-Kyung LEE, Won-Seok CHO
  • Patent number: 9112045
    Abstract: A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Hyung Kim, Chang-Seok Kang, Woon-Kyung Lee
  • Patent number: 9087861
    Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: July 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Woon-Kyung Lee, Won-Seok Cho
  • Publication number: 20150064902
    Abstract: A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n?1 first recesses penetrating 20 through 2n?1 deposited sacrificial layers and forming a buried insulating layer group including 2n?1 buried insulating layers filling the 2n?1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n?1 buried insulating layers may be formed.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventors: Sang-yong Park, Woon-kyung Lee, Jin-taek Park
  • Patent number: 8933517
    Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers may be directly over a dummy well.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-yean Oh, Woon-kyung Lee
  • Patent number: 8906805
    Abstract: A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n?1 first recesses penetrating 20 through 2n?1 deposited sacrificial layers and forming a buried insulating layer group including 2n?1 buried insulating layers filling the 2n?1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n?1 buried insulating layers may be formed.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yong Park, Woon-kyung Lee, Jin-taek Park
  • Patent number: 8836020
    Abstract: A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ld.
    Inventors: Ju-young Lim, Woon-kyung Lee, Jae-joo Shim, Hui-chang Moon, Sung-min Hwang
  • Publication number: 20140199815
    Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 17, 2014
    Inventors: Sung-Min HWANG, Han-Soo KIM, Woon-Kyung LEE, Won-Seok CHO
  • Publication number: 20140197546
    Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 17, 2014
    Inventors: Sung-Min HWANG, Young-Ho LEE, Seong-Soon CHO, Woon-Kyung LEE
  • Publication number: 20140197481
    Abstract: A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 17, 2014
    Inventors: Sung-Min HWANG, Han-Soo KIM, Woon-Kyung LEE, Won-Seok CHO
  • Publication number: 20140084376
    Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers may be directly over a dummy well.
    Type: Application
    Filed: November 27, 2013
    Publication date: March 27, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-yean Oh, Woon-kyung Lee
  • Patent number: RE47169
    Abstract: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Yean Oh, Woon-Kyung Lee, Seung-Chul Lee