Abstract: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

Abstract: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

Abstract: A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole.

Abstract: A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers.

Abstract: A method of fabricating a flash memory device includes forming a device isolation layer at a predetermined region of a semiconductor substrate having a cell array region and a peripheral circuit region. The device isolation layer defines a first active region and a second active region in the cell array region and the peripheral circuit region, respectively. A gate conductive layer is formed on the entire surface of the semiconductor substrate having the device isolation layer. The gate conductive layer is patterned to form a floating gate pattern covering the first active region. At this time, the peripheral circuit region is still covered with the gate conductive layer. An inter-gate dielectric layer and a control gate conductive layer are formed on the entire surface of the substrate including the floating gate pattern.

Abstract: A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole.

Abstract: A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole.

Abstract: A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers.

Abstract: Disclosed is a method for fabricating a NOR flash memory device where a buried common source line made of an impurity diffusion layer has an even surface or a lower step difference. The method includes forming adjacent isolation layers that define an active region there between within a semiconductor substrate. Then, a floating gate pattern is formed overlying the active region. An inter-gate dielectric film and a control gate film are sequentially formed overlying the floating gate pattern. The control gate film, the inter-gate dielectric film, and the floating gate pattern are sequentially patterned, thereby forming a plurality of word lines extending across the active region. The active region between the adjacent isolation layers and the isolation layers are removed, adjacent to one sidewall of the word lines, thereby forming a common source line region. Next, impurities are implanted into the common source line region, thereby forming a common source line made of an impurity diffusion layer.

Abstract: In a cell array region of a NOR-type mask ROM device and a fabricating method therefor, following formation of a plurality of word lines parallel to one another on a semiconductor substrate, a plurality of sub-bit lines intersecting the top portion of the plurality of word lines at right angles are formed. Trench regions are formed on the semiconductor substrate exposed by the plurality of word lines and the plurality of sub-bit lines. An interlayer insulating layer is formed on the entire surface of the resulting material, and a plurality of bit lines which are parallel to one another are formed on the interlayer insulating layer.

Abstract: A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole.

Abstract: The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a semiconductor substrate, a gate stack formed on the semiconductor substrate. The gate stack has a sidewall and a top surface. A multi-layer sidewall spacer structure is formed on the sidewall of the gate stack. The multi-layer sidewall spacer structure includes a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer that are sequentially stacked. With the present invention, even if the second nitride layer is perforated or damaged during the formation of contact holes, sidewalls of the gate stack of nonvolatile memory cell can be protected with the first nitride layer from mobile ions. Also, etching damage to source/drain regions or field regions can be reduced.

Abstract: A method of manufacturing a flash memory device is characterized by preventing photoresist patterns from being formed directly on or removed directly from a surface of the substrate or the dielectric layer. This is accomplished by separately forming a control gate layer of transistors in a cell area of the substrate and a gate layer of transistors in a peripheral circuit area of the substrate. The method of the present invention includes the steps of forming in a peripheral circuit area of the substrate a gate insulating layer for both high and low voltage regions of the peripheral circuit area and then forming the gate conduction layer on the gate insulating layer. The method of the present invention further comprises the steps of forming in a cell area of the substrate a transistor structure composed of a tunneling gate insulating layer, a floating gate layer, a dielectric layer, and a control gate layer.

Abstract: The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a semiconductor substrate, a gate stack formed on the semiconductor substrate. The gate stack has a sidewall and a top surface. A multi-layer sidewall spacer structure is formed on the sidewall of the gate stack. The multi-layer sidewall spacer structure includes a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer that are sequentially stacked. With the present invention, even if the second nitride layer is perforated or damaged during the formation of contact holes, sidewalls of the gate stack of nonvolatile memory cell can be protected with the first nitride layer from mobile ions. Also, etching damage to source/drain regions or field regions can be reduced.

Abstract: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

Abstract: In a cell array region of a NOR-type mask ROM device and a fabricating method therefor, following formation of a plurality of word lines parallel to one another on a semiconductor substrate, a plurality of sub-bit lines intersecting the top portion of the plurality of word lines at right angles are formed. Trench regions are formed on the semiconductor substrate exposed by the plurality of word lines and the plurality of sub-bit lines. An interlayer insulating layer is formed on the entire surface of the resulting material, and a plurality of bit lines which are parallel to one another are formed on the interlayer insulating layer.

Abstract: A method of fabricating a flash memory device includes forming a device isolation layer at a predetermined region of a semiconductor substrate having a cell array region and a peripheral circuit region. The device isolation layer defines a first active region and a second active region in the cell array region and the peripheral circuit region, respectively. A gate conductive layer is formed on the entire surface of the semiconductor substrate having the device isolation layer. The gate conductive layer is patterned to form a floating gate pattern covering the first active region. At this time, the peripheral circuit region is still covered with the gate conductive layer. An inter-gate dielectric layer and a control gate conductive layer are formed on the entire surface of the substrate including the floating gate pattern.

Abstract: Disclosed is a method for fabricating a NOR flash memory device where a buried common source line made of an impurity diffusion layer has an even surface or a lower step difference. The method includes forming adjacent isolation layers that define an active region there between within a semiconductor substrate. Then, a floating gate pattern is formed overlying the active region. An inter-gate dielectric film and a control gate film are sequentially formed overlying the floating gate pattern. The control gate film, the inter-gate dielectric film, and the floating gate pattern are sequentially patterned, thereby forming a plurality of word lines extending across the active region. The active region between the adjacent isolation layers and the isolation layers are removed, adjacent to one sidewall of the word lines, thereby forming a common source line region. Next, impurities are implanted into the common source line region, thereby forming a common source line made of an impurity diffusion layer.

Abstract: In a cell array region of a NOR-type mask ROM device and a fabricating method therefor, following formation of a plurality of word lines parallel to one another on a semiconductor substrate, a plurality of sub-bit lines intersecting the top portion of the plurality of word lines at right angles are formed. Trench regions are formed on the semiconductor substrate exposed by the plurality of word lines and the plurality of sub-bit lines. An interlayer insulating layer is formed on the entire surface of the resulting material, and a plurality of bit lines which are parallel to one another are formed on the interlayer insulating layer.

Abstract: A method of manufacturing a flash memory device is characterized by preventing photoresist patterns from being formed directly on or removed directly from a surface of the substrate or the dielectric layer. This is accomplished by separately forming a control gate layer of transistors in a cell area of the substrate and a gate layer of transistors in a peripheral circuit area of the substrate. The method of the present invention includes the steps of forming in a peripheral circuit area of the substrate a gate insulating layer for both high and low voltage regions of the peripheral circuit area and then forming the gate conduction layer on the gate insulating layer. The method of the present invention further comprises the steps of forming in a cell area of the substrate a transistor structure composed of a tunneling gate insulating layer, a floating gate layer, a dielectric layer, and a control gate layer.