Abstract: Provided is a bonding wire for a semiconductor package, which includes an insulating layer formed on the outer surface of a core portion by a thin layer deposition method, so that the occurrence of a short-circuit during wire bonding is fundamentally prevented and bondability is improved. The bonding wire for a semiconductor package comprises: a core portion formed of a conductive metal; and an insulating layer formed on the outer surface of the core portion by a thin layer deposition method.

Abstract: Disclosed is a method of purifying carbon nanotubes, including treating carbon nanotubes with an inert gas at a high temperature in a low vacuum in a reactor and obtaining ultrapure carbon nanotubes, wherein the ultrapure carbon nanotubes contain 50 ppm or less of each metal remaining therein.

Abstract: Disclosed is a method of efficiently separating 1,3-butadiene and methylethylketone, which are compounds of interest, from byproducts or impurities in the dehydration products of 2,3-butanediol so as to recover the compounds of interest at high purity.

Abstract: Disclosed is a method of purifying carbon nanotubes, including treating carbon nanotubes with an inert gas at a high temperature in a low vacuum in a reactor and obtaining ultrapure carbon nanotubes, wherein the ultrapure carbon nanotubes contain 50 ppm or less of each metal remaining therein.

Abstract: Disclosed is a method of efficiently separating 1,3-butadiene and methylethylketone, which are compounds of interest, from byproducts or impurities in the dehydration products of 2,3-butanediol so as to recover the compounds of interest at high purity.

Abstract: Disclosed is a horizontal-type atomic layer deposition apparatus for large-area substrates, in which a plurality of large-area substrates can be simultaneously subjected to an atomic layer deposition process in a state in which they are stacked in a horizontal position. The apparatus comprises: an outer chamber that is maintained in a vacuum state; an inner chamber provided in the outer chamber; a chamber cover configured to move upward and downward to open and close the bottom of the inner chamber; a cassette configured to move upward and downward with the chamber cover; a process gas injecting portion configured to inject a process gas into a space between a plurality of substrates loaded in the cassette; a gas discharge portion configured to suck and discharge the process gas; and a substrate introducing/discharging means configured to introduce the substrates into the outer chamber and discharge the substrates.

Abstract: Disclosed is an apparatus for batch-type large-area atomic layer deposition, which can perform an atomic layer deposition process on a plurality of large-area glass substrates. The apparatus comprises: a vacuum chamber; gate valves provided at both sides of the vacuum chamber; a process gas supply unit provided in the upper portion of the vacuum chamber and configured to inject laminar-flow process gas downward; a gas discharge unit provided in the lower portion of the vacuum chamber and configured to discharge gas from the vacuum chamber; a cassette configured to load a plurality of substrates and disposed between the process gas supply unit and the gas discharge unit; and an elevating unit provided at the side of the gas discharge unit in the vacuum chamber and configured in the vacuum chamber to elevate the cassette so as to bring the cassette into close contact with the process gas supply unit.

Abstract: A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown directly on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown directly on the lower electrode.

Abstract: Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH.

Abstract: Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a crystalline auxiliary layer on the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer. Forming the crystalline auxiliary layer may include forming an amorphous auxiliary layer on the amorphous aluminum oxide layer; and crystallizing the amorphous auxiliary layer.

Abstract: A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown on the lower electrode.

Abstract: A method of forming a phase change layer using a Ge compound and a method of manufacturing a phase change memory device using the same are provided. The method of manufacturing a phase change memory device included supplying a first precursor on a lower layer on which the phase change layer is to be formed, wherein the first precursor is a bivalent precursor including germanium (Ge) and having a cyclic structure. The first precursor may be a cyclic germylenes Ge-based compound or a macrocyclic germylenes Ge-based, having a Ge—N bond. The phase change layer may be formed using a MOCVD method, cyclic-CVD method or an ALD method. The composition of the phase change layer may be controlled by a deposition pressure in a range of 0.001 torr-10 torr, a deposition temperature in a range of 150° C. to 350° C. and/or a flow rate of a reaction gas in the range of 0-1 slm.

Abstract: A method of forming a phase change layer may include providing a bivalent first precursor having germanium (Ge), a second precursor having antimony (Sb), and a third precursor having tellurium (Te) onto a surface on which the phase change layer is to be formed. The phase change layer may be formed by CVD (e.g., MOCVD, cyclic-CVD) or ALD. The composition of the phase change layer may be varied by modifying the deposition pressure, deposition temperature, and/or supply rate of reaction gas. The deposition pressure may range from about 0.001-10 torr, the deposition temperature may range from about 150-350° C., and the supply rate of the reaction gas may range from about 0-1 slm. Additionally, the above phase change layer may be provided in a via hole and bounded by top and bottom electrodes to form a storage node.

Abstract: A method of surface treating a phase change layer may include, before forming the phase change layer, forming a coating layer on a surface of a bottom layer on which the phase change layer is to be formed, wherein the coating layer has a chemical structure for contributing to the adherence of an alkyl radical to the surface of the bottom layer. After forming the coating layer, the phase change layer may be formed using an atomic layer deposition (ALD) method.

Abstract: Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer.

Abstract: A phase change memory device and a method of manufacturing the phase change memory device are provided. The phase change memory device may include a switching element and a storage node connected to the switching element, wherein the storage node includes a bottom electrode and a top electrode, a phase change layer interposed between the bottom electrode and the top electrode, and a titanium-tellurium (Ti—Te)-based diffusion barrier layer interposed between the top electrode and the phase change layer. The Ti—Te based diffusion barrier layer may be a TixTe1?x layer wherein x may be greater than 0 and less than 0.5.

Abstract: Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change layer includes indium with a concentration ranging from about 5 at % to about 15 at %. The phase change layer may be a GST layer that includes indium. The phase change layer may be a GST layer that includes gallium.

Abstract: A method of fabricating a phase change RAM (PRAM) having a fullerene layer is provided. The method of fabricating the PRAM may include forming a bottom electrode, forming an interlayer dielectric film covering the bottom electrode, and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film, forming a bottom electrode contact plug by filling the bottom electrode contact hole with a plug material, forming a fullerene layer on a region including at least an upper surface of the bottom electrode contact plug and sequentially stacking a phase change layer and an upper electrode on the fullerene layer. The method may further include forming a switching device on a substrate and a bottom electrode connected to the switching device, forming an interlayer dielectric film covering the bottom electrode and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film.

Abstract: Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH.

Abstract: Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a crystalline auxiliary layer on the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer. Forming the crystalline auxiliary layer may include forming an amorphous auxiliary layer on the amorphous aluminum oxide layer; and crystallizing the amorphous auxiliary layer.