Abstract: Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer.

Abstract: Provided are a gate stack, a capacitorless dynamic random access memory (DRAM) including the gate stack and methods of manufacturing and operating the same. The gate stack for a capacitorless DRAM may include a tunnel insulating layer on a substrate, a first charge trapping layer on the tunnel insulating layer, an interlayer insulating layer on the first charge trapping layer, a second charge trapping layer on the interlayer insulating layer, a blocking insulating layer on the second charge trapping layer, and a gate electrode on the blocking insulating layer. The capacitorless DRAM may include the gate stack on the substrate, and a source and a drain in the substrate on both sides of the gate stack.

Abstract: A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown on the lower electrode.

Abstract: Provided are a phase change memory device and a method of fabricating the same. The phase change memory device including a phase change layer in a storage node thereof includes: a bottom electrode; a bottom electrode contact layer formed of a phase change material disposed on the bottom electrode; a first phase change layer having a smaller width than the bottom electrode contact layer, disposed on the bottom electrode contact layer; a second phase change layer having a larger width than the first phase change layer, disposed on the first phase change layer; and a upper electrode disposed on the second phase change layer.

Abstract: Provided are a method of forming a phase change layer, a method of manufacturing a storage node using the method of forming a phase change layer, and a method of manufacturing a phase change memory device using the method of manufacturing a storage node. The method of forming a phase change layer may use an electrochemical deposition (ECD) method. The method of forming the phase change layer may include forming an electrolyte by mixing a solvent and precursors, each precursor containing an element of the phase change layer, dipping an anode plate and a cathode plate in the electrolyte to be spaced apart from each other, wherein the cathode plate may be a substrate on which the phase change layer is to be deposited, setting deposition conditions of the phase change layer; and supplying a voltage between the anode plate and the cathode plate.

Abstract: A phase change material layer is a single layer including an upper layer portion and a lower layer portion. Crystal lattices of the upper layer portion and the lower layer portion are different. The phase change material layer is formed by forming a doped lower layer by supplying a first source with a doping gas to a substrate. The supply of the doping gas is stopped and an undoped upper layer is formed by supplying a second source onto the lower layer. The upper layer and the lower layer are formed such that crystal lattices of the upper and lower layers are different.

Abstract: A phase change memory device and a method of manufacturing the phase change memory device are provided. The phase change memory device may include a switching element and a storage node connected to the switching element, wherein the storage node includes a bottom electrode and a top electrode, a phase change layer interposed between the bottom electrode and the top electrode, and a titanium-tellurium (Ti—Te)-based diffusion barrier layer interposed between the top electrode and the phase change layer. The Ti—Te based diffusion barrier layer may be a TixTe1-x layer wherein x may be greater than 0 and less than 0.5.

Abstract: A method of forming a phase change layer using a Ge compound and a method of manufacturing a phase change memory device using the same are provided. The method of manufacturing a phase change memory device included supplying a first precursor on a lower layer on which the phase change layer is to be formed, wherein the first precursor is a bivalent precursor including germanium (Ge) and having a cyclic structure. The first precursor may be a cyclic germylenes Ge-based compound or a macrocyclic germylenes Ge-based, having a Ge—N bond. The phase change layer may be formed using a MOCVD method, cyclic-CVD method or an ALD method. The composition of the phase change layer may be controlled by a deposition pressure in a range of 0.001 torr-10 torr, a deposition temperature in a range of 150° C. to 350° C. and/or a flow rate of a reaction gas in the range of 0-1 slm.

Abstract: A method of forming a phase change layer may include providing a bivalent first precursor having germanium (Ge), a second precursor having antimony (Sb), and a third precursor having tellurium (Te) onto a surface on which the phase change layer is to be formed. The phase change layer may be formed by CVD (e.g., MOCVD, cyclic-CVD) or ALD. The composition of the phase change layer may be varied by modifying the deposition pressure, deposition temperature, and/or supply rate of reaction gas. The deposition pressure may range from about 0.001-10 torr, the deposition temperature may range from about 150-350° C., and the supply rate of the reaction gas may range from about 0-1 slm. Additionally, the above phase change layer may be provided in a via hole and bounded by top and bottom electrodes to form a storage node.

Abstract: A method of surface treating a phase change layer may include, before forming the phase change layer, forming a coating layer on a surface of a bottom layer on which the phase change layer is to be formed, wherein the coating layer has a chemical structure for contributing to the adherence of an alkyl radical to the surface of the bottom layer. After forming the coating layer, the phase change layer may be formed using an atomic layer deposition (ALD) method.

Abstract: Provided are a method of manufacturing a thin film structure, a method of manufacturing a storage node having the same, a method of manufacturing a phase-change random access memory device having the same and a thin film structure, storage node and phase-change random access memory device formed using the same. The method of manufacturing the thin film structure may include the operations of obtaining a seed layer formed of a chalcogenide alloy, by supplying one or two selected from the group consisting of a Group IV-precursor, a Group V-precursor, and a Group VI-precursor to an upper surface of an amorphous material layer, and forming the thin film by supplying a Group IV-precursor, a Group V-precursor, and a Group VI-precursor to an upper surface of the seed layer.

Abstract: Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change layer includes indium with a concentration ranging from about 5 at % to about 15 at %. The phase change layer may be a GST layer that includes indium. The phase change layer may be a GST layer that includes gallium.

Abstract: A method of forming a phase change material thin film comprises supplying a first precursor including Ge and a second precursor including Te into a reaction chamber concurrently to form a GeTe thin film on a substrate. A second precursor including Te and a third precursor including Sb are concurrently supplied into the reaction chamber and onto the GeTe thin film to form a SbTe thin film. The supplying of the first and second precursors and the supplying of the second and third precursors to form a GeSbTe thin film.

Abstract: A method of fabricating a phase change RAM (PRAM) having a fullerene layer is provided. The method of fabricating the PRAM may include forming a bottom electrode, forming an interlayer dielectric film covering the bottom electrode, and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film, forming a bottom electrode contact plug by filling the bottom electrode contact hole with a plug material, forming a fullerene layer on a region including at least an upper surface of the bottom electrode contact plug and sequentially stacking a phase change layer and an upper electrode on the fullerene layer. The method may further include forming a switching device on a substrate and a bottom electrode connected to the switching device, forming an interlayer dielectric film covering the bottom electrode and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film.

Abstract: A multibit phase change memory device structured such that a plurality of individual phase change memory devices are aligned in a plan area or vertically, and a method of driving the same are provided. The multibit phase change memory device includes a phase change material layer having a plurality of contact portions being in contact with a heating electrode, and having a plurality of active regions, each active region forming a unit phase change memory device. The phase change material layer may be composed of one material layer in which the plurality of active regions are aligned in plural arrays. Alternatively, the phase change material layer may be composed of a plurality of phase change material layers in which one or plural active regions are respectively aligned in one array. The plurality of phase change material layers may be disposed in a same level of a plan area, or the plurality of phase change material layers may be respectively disposed on different plan areas in a same vertical line.

Abstract: Provided is a gate structure including a multi-tunneling layer and method of fabricating the same. Also provided is a nanodot semiconductor memory device including such gate structure and method of fabricating the same. The gate structure may include a first insulation layer, a second insulation layer, a charge storage layer including nanodots and formed on the second insulation layer, a third insulation layer formed on the charge storage layer, and a gate electrode layer formed on the third insulation layer. There may also be a nanodot semiconductor memory device including a semiconductor substrate, in which a first impurity region and a second impurity region may be formed, and including the gate structure formed on the semiconductor substrate which contacts the first and second impurity regions.