Abstract: A method of fabricating a nonvolatile memory device having a first conductivity type substrate, includes the steps of forming a gate insulating layer on the entire surface of the semiconductor substrate, forming a plurality of floating gate lines on the gate insulating layer, forming first sidewall spacers on both sides of each floating gate, forming a plurality of impurity regions having a second conductivity type in the substrate between the floating gate lines, forming a dielectric layer on the floating gate lines, forming a plurality of control gate lines on the dielectric layer, forming second sidewall spacers on both sides of the control gate lines, selectively etching the dielectric layer and the floating gate lines to form a plurality of floating gates, forming tunneling insulating layers on both sides of the floating gates, and forming a plurality of program lines between the impurity regions.

Abstract: Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate, source and drain respectively for varying a charge amount in the floating gate. A channel in a transistor is turned off at an initial stage and then turned on thereafter, and at least one of the voltages applied to the control gate and the program/select gate is halted to stop the programming when a conductivity of the channel region reaches a reference value.

Abstract: Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate, source and drain respectively for varying a charge amount in the floating gate. A channel in a transistor is turned off at an initial stage and then turned on thereafter, and at least one of the voltages applied to the control gate and the program/select gate is halted to stop the programming when a conductivity of the channel region reaches a reference value.

Abstract: Sensing circuit for a semiconductor device and a sensing method using the same which allows sensing of a selected nonvolatile memory cell at a low voltage, a low power, and a fast speed, and has a high sensing reliability, the circuit including a bitline connected to a drain terminal of a memory cell through a Y-decoder, a senseline for sensing, and forwarding a data in the memory cell, a switching unit for switching between the bitline and the senseline, a first current supply unit disposed between a power source and the bitline for supplying a current to the bitline to the memory cell, a second current supply unit disposed between the power source and the senseline for supplying a current to the senseline, a voltage level shifter for providing a voltage difference between the bitline and the senseline, and a sense MOS transistor disposed between the senseline and the ground voltage and having a gate terminal connected to one end of the voltage level shifter.

Abstract: A method is provided for fabricating a nonvolatile memory device having a simple stacked stricture with program gates. The method includes forming bitlines of second conductivity type along a first direction separated by a first prescribed distance in a substrate of a first conductivity type and forming first lines on the substrate along a second direction separated from one another by a second prescribed distance. The second direction is substantially perpendicular to the first direction, and the first lines include a first conductive layer on an isolating layer. A gate insulating layer is formed on the substrate and a tunneling insulating layer on the first conductive lines and a second conductive layer is formed on the entire surface. The second conductive layer, the tunneling insulating layer, and the first conductive lines are selectively removed to form second conductive lines along the first direction and program gates.

Abstract: A method of fabricating a nonvolatile memory device having a substrate, includes the steps of forming a plurality of bit lines in the substrate, forming a plurality of field oxide layers on the substrate perpendicular to the bit lines, forming a gate insulating layer on an entire surface of the substrate including the bit lines and the field oxide layers, forming a plurality of floating lines on the gate insulating layer between the bit lines, forming a dielectric layer on the entire surface of the semiconductor substrate including the floating line's and the gate insulating layer, forming a plurality of word lines between the field oxide layer perpendicular to the bit lines, forming sidewall spacer at both sides of the word lines, selectively removing the dielectric layer and the floating lines using the word lines and the sidewall spacer as masks to form a plurality of floating gates, forming a tunneling layer at both sides of the floating gates, and forming a plurality of program lines between the bit line

Abstract: A system for programming a nonvolatile memory includes a plurality of memory cells each having a field effect transistor with a control gate, a drain, a source, and a charge storage region, voltage sources for applying preset voltages pertinent to a threshold level to the source, the drain, and the control gate in each of the memory cells, a monitor for monitoring a current flowing through a channel in each of the memory cells, and a controller for stopping at least one of the voltages applied to the source, the drain, and the control gate in each of the memory cells when the monitor senses that the current flowing through the channel in the memory cell reaches a reference current.

Abstract: A device and method for sensing data in a multi-bit memory cell of a memory cell array unit is provided where each memory cell has at least two threshold voltage levels. The device can include a multistep current source unit to provide quantized voltages, each having a width smaller than a threshold voltage distribution in a selected memory cell, according to a current flowing through the selected memory cell. An analog-to-digital converter compares the quantized voltages from the multistep current source unit with a plurality of reference voltages to provide a state of the memory cell in binary form. The device and method for sensing data in the multi-bit memory cell uses the quantized voltages to increase sensing reliability, increases sensing speed and increases a gap between the quantized voltages relative to the threshold voltage distribution.

Abstract: Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate, source and drain respectively for varying a charge amount in the floating gate. A channel in a transistor is turned off at an initial stage and then turned on thereafter, and at least one of the voltages applied to the control gate and the program/select gate is halted to stop the programming when a conductivity of the channel region reaches a reference value.

Abstract: A non-volatile memory device and a method of fabricating the same are disclosed. The non-volatile memory device includes a semiconductor substrate having a first conductive type, a plurality of first, second and third impurity regions having a second conductive type in the substrate, a plurality of first insulating layer only on the substrate between the second and third impurity regions, a second insulating layer on the substrate except on the first insulating layer formed, a plurality of floating gate on the first and second insulating layers, a plurality of dielectric layer on the floating gate, a plurality of control gate on the dielectric layer.

Abstract: A device for sensing a data in a multibit memory cell includes a reference voltage generating part for generating a plurality of reference voltages, a switching part for successively applying the plurality of reference voltages from the reference voltage generating part to a control gate on the multibit memory cell, a sensing part for comparing the data recorded in the multibit memory cell to the reference voltages when each of the plurality of reference voltages is applied thereto, a controlling part for generating a plurality of reference voltage selection signals to control the switching part, and applying a highest reference voltage to the clock signal controlling part so that the data is produced in response to a clock signal from the clock signal controlling part, and a clock signal controlling part for subjecting a signal from the sensing part and a highest reference voltage selecting signal to a logical operation in controlling an external main clock signal, and a latching part for latching the data f

Abstract: An array of a nonvolatile memory device and a fabricating method thereof has a simple stacked-gate structure without metal contact holes. The array of a nonvolatile memory device includes a plurality of memory cells. Each memory cell includes a floating gate, a control gate, and the source/drain regions. A plurality of word lines are connected to the control gates of the memory in a column direction and spaced apart from one another by a predetermined distance in a row direction. A plurality of bit lines are connected to the source/drain regions perpendicular to the word lines. A plurality of program lines is formed in parallel with the bit lines. A plurality of program gates is connected to the program lines for programming the floating gates adjacent to the program gates.

Abstract: A nonvolatile memory cell includes a floating gate; a programming region, having a first current path to the floating gate, for programming by providing charge carriers to the floating gate through the first current path or extracting charge carriers stored in the floating gate; and a verification region, having a second current path separated from the first current path, for verifying the charge amount of the floating gate through the second current path during programming.

Abstract: A method of at least one of programming and verifying a threshold voltage of a nonvolatile memory cell. The memory cell includes a control gate, a floating gate, a drain, a source, and a channel region between the drain and the source. The method is a voltage-type programming compared to a current type programming. A first voltage, which varies in correspondence to each threshold level programming, is applied to the control gate, and second and third voltages are applied to the drain and the source, respectively, so that the channel region is turned off at an initial stage and charge carriers for the programming are transferred from the floating gate to the drain. A conductivity of the channel region is monitored during each threshold level programming.

Abstract: A nonvolatile memory device includes a floating gate for storing a charge carrier during programming, a program gate coupled to the floating gate and performing programming by injecting the charge carrier induced from the outside during programming into the floating gate, an erasure gate coupled to the floating gate and emitting the charge carrier stored in the floating gate to the outside during erasure to outside, a control gate coupled to the floating gate and controlling an amount of the charge carrier provided from the program gate to the floating gate during programming, and a transistor coupled to the floating gate and verifying the amount of the charge carrier provided form the program gate during programming, the transistor including a channel region and source and drain regions.

Abstract: A nonvolatile memory device includes a plurality of program/select lines arranged in a row direction spaced apart from each other in first prescribed intervals, a plurality of bit lines arranged in a column direction spaced apart from each other in second prescribed intervals at a substantially right angle to the plurality of the program/select lines to form a matrix of a plurality of square areas, and a plurality of control lines disposed in the column direction and adjacent to the bit lines in a one-to-one correspondence. Each cell is disposed in one of the square areas, and has a source, a drain, and a channel region. Further, a select/program gate of each cell allows the selection of the cell for programming and conducting the programming by means of charge carriers. A floating gate stores the charge carriers by means of tunneling through the channel region during erasure and provides the stored charge carriers to the program/select gate through the tunneling diode during programming.

Abstract: A data sensing apparatus and method of a multi-bit memory cell includes a first step of generating 2.sup.

Abstract: A device for and method of sensing data of a multi-bit memory cell includes a memory cell having a gate, a source and a drain, the memory cell being programmed with at least two voltage levels, a voltage generator coupled to the memory cell and providing the gate of the memory cell with a voltage, the voltage being increased linearly, a sensing amplifier coupled to the memory cell and generating a sensing signal when a drain voltage of the memory cell is lower than a reference voltage, a voltage detector coupled to the sensing amplifier and the voltage generator and detecting synchronously a gate voltage of the memory cell with the sensing signal of the sensing amplifier, andan A/D converter coupled to the voltage detector and translating the gate voltage detected in the voltage detector into a digital value.

Abstract: A nonvolatile memory cell includes a floating gate; a programming region, having a first current path to the floating gate, for programming by providing charge carriers to the floating gate through the first current path or extracting charge carriers stored in the floating gate; and a verification region, having a second current path separated from the first current path, for verifying the charge amount of the floating gate through the second current path during programming.

Abstract: A method for programming a nonvolatile memory cell having a control gate, a floating gate, a drain, a source, and a channel region disposed between the drain and source, the method includes the steps of applying a first voltage to the control gate to form an inversion layer in the channel region, the first voltage being varied to program at least two threshold levels of the memory cell, applying a second voltage to the drain and a third voltage to the source, the second voltage being greater than the third voltage, monitoring a current flowing between the drain and the source during the programming of the at least two threshold levels, and terminating any one of the first voltage, the second voltage, and the third voltage when the monitored current reaches a preset reference current to thereby stop the programming of the at least two threshold levels.