Abstract: A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Abstract: A refrigerator having improved space utilization includes a main body, a storage room formed inside of the main body, a center frame provided at the center of the storage room to be spaced apart from both side walls of the storage room and having a guide elongated in a front-rear direction of the storage room and a plurality of shelves detachably coupled to the guide so as to be movable along the guide, the plurality of shelves including a first shelf and a second shelf positioned under the first shelf while the second shelf moving along the same guide as the first shelf in an inverted state.

Abstract: A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.

Abstract: Provided is a multi network and method to transmit packets. The multi network includes a mesh network, a tree network, and a network interface connected to the mesh network and the tree network and configured to transmit, through the mesh network and the tree network, a packet generated by a processing unit, of a processing system having plural processing units, at a starting point to a destination point for another processing unit of the processing system and configured to selectively inject the packet into one of the mesh network and the tree network to transmit the packet to the other processing unit.

Abstract: Provided is a processor including a plurality of devices. The processor includes a source processing device configured to identify data to request from another device, and a destination processing device configured to, in response to a request for the identified data from the source processing device using credit-based flow control, transmit the identified data to the source processing device using the credit-based flow control. The source processing device includes a credit buffer used for the credit-based flow control, the credit buffer being allocable to include a cache region configured to cache the transmitted identified data received by the source processing device.

Abstract: A texture cache architecture includes a first texture cache to store compressed texel data and a second texture cache to store decompressed texel data. A controller schedules accesses to access texel data from the first or second texture cache. The second texture cache permits decompressed texel data to be reused for more than one texel access request.

Abstract: A refrigerator having improved space utilization includes a main body, a storage room formed inside of the main body, a center frame provided at the center of the storage room to be spaced apart from both side walls of the storage room and having a guide elongated in a front-rear direction of the storage room and a plurality of shelves detachably coupled to the guide so as to be movable along the guide, the plurality of shelves including a first shelf and a second shelf positioned under the first shelf while the second shelf moving along the same guide as the first shelf in an inverted state.

Abstract: A method of executing a graphics pipeline includes calculating, while executing the graphics pipeline on a current frame, a resource for processing properties of an object included in a following frame, determining, based on a result of the calculating, whether to perform a pre-process for the object included in the following frame, performing the pre-processing, when the pre-process is determined to be performed, comprising transforming the properties of the object that are to be processed in a graphics pipeline for the following frame, and executing, when the pre-process is to be performed, the graphics pipeline for the following frame by using the transformed properties of the object.

Abstract: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

Abstract: A semiconductor element includes a semiconductor region (11) of a first conductivity type, a buried charge-generation region (16) of a second conductivity type, buried in an upper portion of the semiconductor region (11) to implement a photodiode (D1) together with the semiconductor region (11) to generate charges, a charge-readout region (15) of the second conductivity type, provided in the semiconductor region (11) to accumulate the charges transferred from the buried charge-generation region (16), and a reset-performing region (12) of the second conductivity type, provided in the semiconductor region (11), a variable voltage is applied to the reset-performing region (12) to change the height of a potential barrier generated in the semiconductor region (11) sandwiched between the charge-readout region (15) and the reset-performing region (12) to exhaust the charges accumulated in the charge-readout region (15).

Abstract: A texture cache architecture facilitates access of compressed texture data in non-power of two formats, such as the Adaptive Scalable Texture Compression (ASTC) codec. In one implementation, the texture cache architecture includes a controller, a first buffer, a second buffer, and a texture decompressor. A first buffer stores one or more blocks of compressed texel data fetched, in response to a first request, from a first texture cache, where the one or more blocks of compressed texel data including at least requested texel data. The second buffer stores decompressed one or more blocks of compressed texel data and provides the decompressed requested texel data as output to a second texture cache. The one or more blocks of compressed texel data stored by the first buffer includes second texel data in addition to the requested texel data.

Abstract: A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

Abstract: Disclosed herein is a refrigerator having dividers movable in the left-right direction to efficiently use the internal space of a container and enabling a tray or a shelf used in the fridge room to be used in the freezer room as well by preventing the gap between the dividers from narrowing to a certain distance or less to put the tray on the dividers.

Abstract: A processor and corresponding method are described including cores having a thread set allocated based on a pre-set implementation order, and a controller configured to receive scheduling information determined based on an implementation pattern regarding the allocated thread set from one of the cores and transmit the scheduling information to another of the cores. The one of cores determines the scheduling information according to characteristics of an application when implementation of the thread set is completed. Each of the cores re-determines an implementation order regarding the allocated thread set based on the determined scheduling information.

Abstract: A method of managing graphics data in a graphics processing device may include: receiving a first draw call having a first identifier, generating a first lookup table having the first identifier mapped in association with a first handle value by allocating the first handle value to the first identifier, generating a second lookup table having the first handle value mapped in association with a first graphics state setting value by allocating the first handle value to the first graphics state setting value, wherein the first graphics state setting value corresponds to the first identifier, and performing at least one graphics pipeline operation to process the first draw call by using the first graphics state setting value obtained from the second lookup table.

Abstract: A tile-based rendering method includes performing binning of a current frame; generating an identification code of binning information or property information of a tile to be rendered in the current frame; comparing the identification code of the tile to be rendered to an identification code of a previous tile, wherein a location of the previous tile in a previous frame is the same as a location of the tile to be rendered in the current frame; and rendering the current frame by either re-using an image stored in a frame buffer or performing pixel processing of the tile to be rendered depending on a result of the comparing.