Patents by Inventor Woong Sun
Woong Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9579398Abstract: The present invention relates to the pharmaceutical use of FAM19A5 involved in regulating gliogenesis, and more specifically, to the use of FAM19A5 in the prevention, diagnosis, or treatment of central nervous system injuries, degenerative brain diseases, or central nervous system diseases, FAM19A5 being spread in the neural stem cells in vertebrates and regulating gliogenesis.Type: GrantFiled: February 15, 2013Date of Patent: February 28, 2017Assignee: Neuracle Science Co., Ltd.Inventors: Jae Young Seong, Jong Ik Hwang, Woong Sun, Eun Bee Cho, Won-ki Kim
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Patent number: 9335596Abstract: Embodiments of the present invention disclose an array substrate, a display device and a repair method of the array substrate. The array substrate comprises a display region; a peripheral region, in which a peripheral circuit including a plurality of leading wires is provided, and the peripheral region including: an insulation layer, provided above a layer in which the peripheral circuit is provided; and a leading wire repair layer, provided above the insulation layer, wherein the leading wire repair layer includes at least two common repair lines extended along an arrangement direction of the leading wires in the peripheral circuit, and a plurality of repair lines electrically connected the at least two common repair lines are provided between the two adjacent common repair lines.Type: GrantFiled: December 14, 2013Date of Patent: May 10, 2016Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Pijian Jia, Woong Sun Yoon, Zhaohui Hao
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Publication number: 20160035747Abstract: An array substrate and a fabrication method thereof are provided. The array substrate comprises a plurality of wiring regions (S-S?) disposed in a non-display region, a plurality of signal lines (111, 112) is provided in the wiring regions (S-S?), at least part of the signal lines (111, 112) within each of the wiring regions (S-S?) are respectively formed by connecting conducting wires (121, 123) located in different layers in series; and any two of the signal lines (111, 112) within a same wiring region (S-S?) have a resistance difference within a threshold range. The same signal line (111, 112) is disposed in different layers, so that the signal line (111, 112) is bent in a plane perpendicular to the array substrate, which achieves of the extension of a length of the signal line (111, 112), and thus increases the length and resistance of the signal line (111, 112), the resistance of which needs to be increased.Type: ApplicationFiled: July 18, 2014Publication date: February 4, 2016Inventors: Ming ZHANG, Chao FAN, Liquan CUI, Zhaohui HAO, Woong Sun YOON
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Patent number: 9245752Abstract: This present disclosure relates to an atomic layer etching method for graphene, including adsorbing reactive radicals onto a surface of the graphene and irradiating an energy source to the graphene on which the reactive radicals are adsorbed.Type: GrantFiled: January 22, 2014Date of Patent: January 26, 2016Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Geun Young Yeom, Woong Sun Lim, Kyung Seok Min, Yi Yeon Kim, Jong Sik Oh
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Publication number: 20150318305Abstract: An array substrate is disclosed. The array substrate comprises a base substrate (4) and signal lines on the base substrate (4). The signal lines comprises a plurality of conductive layers (11, 12) in different layers, and the plurality of conductive layers (11, 12) are provided with insulation layers (21) therebetween, and are connected in parallel through one or more vias (3). Embodiments of the present disclosure further disclose a method for manufacturing the array substrate.Type: ApplicationFiled: November 29, 2013Publication date: November 5, 2015Applicants: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Ming ZHANG, Zhaohui HAO, Woong Sun YOON
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Publication number: 20150311130Abstract: An array substrate and a display device are provided. The array substrate comprises a display region and a peripheral circuit region (B), wherein a first gate line (20), a first data line (10) and a pixel region are arranged in the display region; the pixel region includes a first pixel electrode and a thin film transistor, and the thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode; the peripheral circuit region (B) is provided with at least one test unit (100) including: a second gate line (101); a second data line (102); a second testing pixel electrode (103); and a second testing thin film transistor (104). The second testing thin film transistor (104) comprises a second gate electrode, a second source electrode and a second drain electrode, wherein the second gate electrode, the second source electrode and the second drain electrode are provided with test ports exposed outside.Type: ApplicationFiled: December 10, 2013Publication date: October 29, 2015Applicants: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Ming ZHANG, Guoqi MAO, Zhaohui HAO, Woong Sun YOON
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Publication number: 20150277198Abstract: Embodiments of the present invention disclose an array substrate, a display device and a repair method of the array substrate. The array substrate comprises a display region; a peripheral region, in which a peripheral circuit including a plurality of leading wires is provided, and the peripheral region including: an insulation layer, provided above a layer in which the peripheral circuit is provided; and a leading wire repair layer, provided above the insulation layer, wherein the leading wire repair layer includes at least two common repair lines extended along an arrangement direction of the leading wires in the peripheral circuit, and a plurality of repair lines electrically connected the at least two common repair lines are provided between the two adjacent common repair lines.Type: ApplicationFiled: December 14, 2013Publication date: October 1, 2015Applicant: BOE TECHNOLOGY GROUP CO., LTDInventors: Pijian Jia, Woong Sun Yoon, Zhaohui Hao
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Patent number: 9021900Abstract: Provided is an in-pipe inspection robot which moves along a path in a pipe to inspect suspected areas such as cracks in the pipe. An in-pipe inspection robot in accordance with an exemplary embodiment of the present invention has a configuration in which two or more operating units having a plurality of arms, which move forward and backward in a radial direction of a pipe, are connected to each other to move in a straight direction or to be bent relative to each other by means of a flexible link mechanism.Type: GrantFiled: September 6, 2012Date of Patent: May 5, 2015Assignee: Industry-Academic Cooperation Foundation Yonsei UniversityInventors: Hyun Seok Yang, Woong Sun Jeon
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Publication number: 20150118230Abstract: The present invention relates to the pharmaceutical use of FAM19A5 involved in regulating gliogenesis, and more specifically, to the use of FAM19A5 in the prevention, diagnosis, or treatment of central nervous system injuries, degenerative brain diseases, or central nervous system diseases, FAM19A5 being spread in the neural stem cells in vertebrates and regulating gliogenesis.Type: ApplicationFiled: February 15, 2013Publication date: April 30, 2015Inventors: Jae Young Seong, Jong Ik Hwang, Woong Sun, Eun Bee Cho, Won-Ki Kim
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Patent number: 8941352Abstract: A contactless charging apparatus of a portable terminal is provided. The contactless charging apparatus of a portable terminal includes a main circuit board, a rectifying unit, a charging unit, and a secondary coil unit mounted on the main circuit board for generating an electromotive force. The secondary coil unit may be formed on the main circuit board in a patterning process instead of an existing copper line coil. A coil layer formed in the patterning process generates an electromotive force induced by a magnetic induction field created by a contactless charger, and a direct current is applied to a battery to charge the battery using the rectifying unit and the charging unit.Type: GrantFiled: May 18, 2011Date of Patent: January 27, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Woong Sun Hong
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Patent number: 8796834Abstract: A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.Type: GrantFiled: May 31, 2011Date of Patent: August 5, 2014Assignee: SK Hynix Inc.Inventors: Jin Ho Bae, Qwan Ho Chung, Woong Sun Lee
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Publication number: 20140206192Abstract: This present disclosure relates to an atomic layer etching method for graphene, including adsorbing reactive radicals onto a surface of the graphene and irradiating an energy source to the graphene on which the reactive radicals are adsorbed.Type: ApplicationFiled: January 22, 2014Publication date: July 24, 2014Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: Geun Young YEOM, Woong Sun LIM, Kyung Seok MIN, Yi Yeon KIM, Jong Sik OH
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Publication number: 20140014958Abstract: A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines.Type: ApplicationFiled: January 9, 2013Publication date: January 16, 2014Applicant: SK HYNIX INC.Inventors: Tac Keun OH, Jae Sung OH, Kwon Whan HAN, Woong Sun LEE, Seon Kwang JEON
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Patent number: 8618637Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.Type: GrantFiled: August 15, 2008Date of Patent: December 31, 2013Assignee: Hynix Semiconductor Inc.Inventors: Han Jun Bae, Woong Sun Lee
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Patent number: 8558380Abstract: A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.Type: GrantFiled: February 3, 2012Date of Patent: October 15, 2013Assignee: SK Hynix Inc.Inventors: Si Han Kim, Woong Sun Lee
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Publication number: 20130236993Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: ApplicationFiled: April 24, 2013Publication date: September 12, 2013Applicant: SK HYNIX INC.Inventors: Woong Sun LEE, Qwan Ho CHUNG
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Patent number: 8445322Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: GrantFiled: September 23, 2011Date of Patent: May 21, 2013Assignee: SK Hynix Inc.Inventors: Woong Sun Lee, Qwan Ho Chung
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Patent number: 8441116Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.Type: GrantFiled: May 7, 2012Date of Patent: May 14, 2013Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Qwan Ho Chung, Il Hwan Cho, Sang Joon Lim, Jong Woo Yoo, Jin Ho Bae, Seung Hyun Lee
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Publication number: 20130104676Abstract: Provided is an in-pipe inspection robot which moves along a path in a pipe to inspect suspected areas such as cracks in the pipe. An in-pipe inspection robot in accordance with an exemplary embodiment of the present invention has a configuration in which two or more operating units having a plurality of arms, which move forward and backward in a radial direction of a pipe, are connected to each other to move in a straight direction or to be bent relative to each other by means of a flexible link mechanism.Type: ApplicationFiled: September 6, 2012Publication date: May 2, 2013Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION YONSEI UNIVERSITYInventors: Hyun Seok YANG, Woong Sun JEON
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Patent number: 8399998Abstract: A semiconductor package includes a semiconductor chip having a first surface, a second surface located opposite the first surface, and side surfaces connecting the first and second surfaces. The semiconductor chip includes bonding pads disposed on the first surface and having a molding member formed to cover the first surface of the semiconductor chip. The molding member is formed so as to expose the side surfaces of the semiconductor chip. The semiconductor chip also includes bonding members having first ends electrically connected to the respective bonding pads and second ends that are connected to and opposite the first ends. The second ends are exposed from side surfaces of the molding member after passing through the molding member so as to allow various electrical connections.Type: GrantFiled: October 23, 2009Date of Patent: March 19, 2013Assignee: Hynix Semiconductor Inc.Inventors: Ki Young Kim, Sung Ho Hyun, Myung Geun Park, Woong Sun Lee