Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof.

Abstract: The present invention relates to a low-viscosity liquid epoxy resin composition and a pressure vessel manufactured using the same, and, more particularly, to a low-viscosity liquid epoxy resin composition, which has good workability due to low viscosity of the epoxy resin composition and exhibits both excellent elongation and an excellent glass transition temperature, and thus is applicable to pressure vessels for compressed natural gas and pressure vessels for compressed hydrogen gas, and a pressure vessel having excellent pressure-resistant characteristics manufactured using the same.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof.

Abstract: A display apparatus is provided. The display apparatus includes a display, a communicator configured to receive a color identification code based on HTML5 from a server, and a processor configured to control the display to display the color identification code and an image corresponding to the color identification code. The color identification code includes information associated with the displayed image and is recognizable by an external apparatus that captures the displayed color identification code.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: An oscillator control circuit includes a zero-temperature coefficient (ZTC) estimator estimating a ZTC voltage based on a supply voltage supplied to the oscillator and a frequency of an oscillation signal output by the oscillator. The ZTC voltage is the magnitude of the supply voltage VDD which corresponds to the ZTC condition for the oscillator. The ZTC estimator generates a bias control signal such that the magnitude of the supply voltage becomes the ZTC voltage.

Abstract: Disclosed are a superconducting current-limiting element for a current limiter and a method of manufacturing a superconducting current-limiting element for a current limiter, in which the current-limiting element is formed in series by stacking linear superconducting wires, or is formed in parallel by stacking superconducting wires so that one or more superconducting wires are disposed in the same layer, thus facilitating the formation of the current-limiting element in series or in parallel and obviating the use of a winding machine when manufacturing the current-limiting element.

Abstract: Temperature sensing circuits are provided. The temperature sensing circuits may include a temperature sensing unit and a buffer unit. The temperature sensing unit may include a transistor that has a first pair of terminals having a first PN junction of the transistor therebetween and a second pair of terminals having a second PN junction of the transistor therebetween. The first pair of terminals are connected together. The temperature sensing unit may output a first temperature sensing voltage comprising a voltage between the second pair of terminals at a first node. The buffer unit may be connected to the first node. The buffer unit may have a cascode follower structure and may output a second temperature sensing voltage that has a magnitude proportional to a magnitude of the first temperature sensing voltage at a second node.

Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Abstract: An oscillator control circuit includes a zero-temperature coefficient (ZTC) estimator estimating a ZTC voltage based on a supply voltage supplied to the oscillator and a frequency of an oscillation signal output by the oscillator. The ZTC voltage is the magnitude of the supply voltage VDD which corresponds to the ZTC condition for the oscillator. The ZTC estimator generates a bias control signal such that the magnitude of the supply voltage becomes the ZTC voltage.

Abstract: An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Abstract: The present invention relates to a low-viscosity liquid epoxy resin composition and a pressure vessel manufactured using the same, and, more particularly, to a low-viscosity liquid epoxy resin composition, which has good workability due to low viscosity of the epoxy resin composition and exhibits both excellent elongation and an excellent glass transition temperature, and thus is applicable to pressure vessels for compressed natural gas and pressure vessels for compressed hydrogen gas, and a pressure vessel having excellent pressure-resistant characteristics manufactured using the same.

Abstract: A display apparatus is provided. The display apparatus includes a display, a communicator configured to receive a color identification code based on HTML5 from a server, and a processor configured to control the display to display the color identification code and an image corresponding to the color identification code. The color identification code includes information associated with the displayed image and is recognizable by an external apparatus that captures the displayed color identification code.

Abstract: An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

Abstract: Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output signal is output, a first transistor which has a drain connected to the output node and is gated by a first signal to increase a voltage level of the output node, a second transistor which has a drain connected to the output node, is gated by a second signal which is a complementary signal of the first signal, and reduces the voltage level of the output node, a pull-up circuit which provides a first compensation current varying according to the voltage level of the output node to a source of the first transistor, and a pull-down circuit which provides a second compensation current varying according to the voltage level of the output node to a source of the second transistor.

Abstract: A display driving circuit includes a fault detector circuit which detects a fault in a circuit device and outputs a fault signal about the fault, a polarity selector circuit which stores polarity selection information and outputs a mode selection signal based on the polarity selection information, and a feedback circuit, wherein the feedback circuit includes an OR gate which receives an inverted signal of the mode selection signal and an inverted signal of the fault signal, an AND gate which receives the inverted signal of the mode selection signal and the fault signal, a first P-type transistor which is turned on or off by an output signal of the OR gate; and a first N-type transistor which is turned on or off by an output signal of the AND gate.

Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.

Abstract: Disclosed are a superconducting current-limiting element for a current limiter and a method of manufacturing a superconducting current-limiting element for a current limiter, in which the current-limiting element is formed in series by stacking linear superconducting wires, or is formed in parallel by stacking superconducting wires so that one or more superconducting wires are disposed in the same layer, thus facilitating the formation of the current-limiting element in series or in parallel and obviating the use of a winding machine when manufacturing the current-limiting element.