Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.

Abstract: MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.

Abstract: The present disclosure provides a deep trench capacitor device. A first capacitor electrode is made up of a doped region of semiconductor substrate in which two or more trenches are arranged. A second capacitor electrode is made up of a continuous body of conductive material. The continuous body of conductive material includes a lower body portion filling the two or more trenches and an upper body portion extending continuously over the lower body portion. The upper body portion extends upwardly out of the trenches by a non-zero distance. A capacitor dielectric liner is arranged in the two or more trenches to separate the first and second capacitor electrodes. The capacitor dielectric liner extends continuously out of the two or more trenches along outer sidewalls of the upper body portion.

Abstract: A method for forming a trench capacitor includes providing a substrate of a semiconductor material having a hard mask layer; etching the hard mask layer and the substrate to form at least one trench extending into the substrate; and performing pull-back etching on the hard mask layer. In the pull-back etching, a portion of the hard mask layer defining and adjacent to side walls of an opening of the at least one trench is removed. A resulting opening on the hard mask layer has a width dimension larger than a width dimension of an opening of the at least one trench extending into the substrate. The method further comprises doping the semiconductor material defining upper surfaces and sidewalls of the at least one trench to form a doped well region.

Abstract: The present disclosure provides a deep trench capacitor device. A first capacitor electrode is made up of a doped region of semiconductor substrate in which two or more trenches are arranged. A second capacitor electrode is made up of a continuous body of conductive material. The continuous body of conductive material includes a lower body portion filling the two or more trenches and an upper body portion extending continuously over the lower body portion. The upper body portion extends upwardly out of the trenches by a non-zero distance. A capacitor dielectric liner is arranged in the two or more trenches to separate the first and second capacitor electrodes. The capacitor dielectric liner extends continuously out of the two or more trenches along outer sidewalls of the upper body portion.

Abstract: The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process. A hard mask is formed over the substrate and etched through the mask to form two or more closely spaced trenches. The hard mask is then reduced by an isotropic etch process. The etch removes the hard mask preferentially between the trenches. Chemical mechanical polishing removes the conductive material down to the remaining hard mask layer, whereby conductive material remains in mask openings and forms a conductive bridge across the trenches.

Abstract: A method for forming a trench capacitor includes providing a substrate of a semiconductor material having a hard mask layer; etching the hard mask layer and the substrate to form at least one trench extending into the substrate; and performing pull-back etching on the hard mask layer. In the pull-back etching, a portion of the hard mask layer defining and adjacent to side walls of an opening of the at least one trench is removed. A resulting opening on the hard mask layer has a width dimension larger than a width dimension of an opening of the at least one trench extending into the substrate. The method further comprises doping the semiconductor material defining upper surfaces and sidewalls of the at least one trench to form a doped well region.

Abstract: The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process. A hard mask is formed over the substrate and etched through the mask to form two or more closely spaced trenches. The hard mask is then reduced by an isotropic etch process. The etch removes the hard mask preferentially between the trenches. Chemical mechanical polishing removes the conductive material down to the remaining hard mask layer, whereby conductive material remains in mask openings and forms a conductive bridge across the trenches.

Abstract: Disclosed is an electrochromic display device comprising: a first and a second substrates; a first and a second electrodes; and an electrochromic composition layer, wherein the device is of a passive matrix drive where the a display and an erasion are performed by an energization in reverse directions between the electrodes, the first and the second electrodes respectively comprise a plurality of electrodes, a pixel is formed where the electrodes are in a grade separated crossing, and the display is performed by voltage application processing where: (i) the first electrode is set as negative, and the second electrode is set as positive, to apply a voltage of a first potential difference, immediately followed by (ii) the first electrode being set as positive, and the second electrode being set as negative, to apply a voltage of a second potential difference equal to or more than the first potential difference.

Abstract: An electrochromic display device including: a first substrate; first electrodes parallely extending on the first substrate; a second substrate opposite to the first substrate; second electrodes parallely extending in a direction orthogonal to the first electrodes on the second substrate; and an electrochromic composition layer between the substrates, wherein the device is passive-matrix driven to perform a display by energization between the electrodes, and to perform erasing of the display by energization in a reverse direction, a pixel is formed in a portion where the first electrodes sterically intersect with the second electrodes, and metal electrical wires extending over the regions between the second electrodes and the second substrate along the second electrodes, each of metal electrical wires being conductively connected to each of the second electrodes corresponding to any one of the regions, and insulated from each of the second electrodes corresponding to the other regions.

Abstract: Disclosed is an electrochromic display device, including, a first substrate, first electrodes provided on an upper surface of the first substrate, a second substrate provided to be opposed to the first substrate above the first substrate, the second substrate being formed of a transparent material, second electrodes provided on an undersurface of the second substrate, at least a part of the second electrodes being formed of a transparent electrode material, and an electrochromic composition layer provided between the first substrate and the second substrate. The electrochromic composition layer contains an electrochromic composition including a supporting electrolyte, a polar solvent, a leuco dye, a hydroquinone derivative and/or a catechol derivative, a ferrocene derivative, and a compound having a carbonyl group.

Abstract: An electrochromic display device including: a first substrate; first electrodes parallely extending on the first substrate; a second substrate opposite to the first substrate; second electrodes parallely extending in a direction orthogonal to the first electrodes on the second substrate; and an electrochromic composition layer between the substrates, wherein the device is passive-matrix driven to perform a display by energization between the electrodes, and to perform erasing of the display by energization in a reverse direction, a pixel is formed in a portion where the first electrodes sterically intersect with the second electrodes, and metal electrical wires extending over the regions between the second electrodes and the second substrate along the second electrodes, each of metal electrical wires being conductively connected to each of the second electrodes corresponding to any one of the regions, and insulated from each of the second electrodes corresponding to the other regions.

Abstract: Disclosed is an electrochromic display device comprising: a first substrate; a first electrode; a second substrate; a second electrode; and an electrochromic composition layer, wherein the device is of a passive matrix drive where the device performs a display by an energization between the electrodes, and performs a erasion of the display, wherein the first electrode comprises electrodes, the second electrode comprises a plurality of transparent display electrodes, a pixel is formed where the electrodes are in a grade separated crossing, at least a surface of the electrodes is respectively oxidized, the electrochromic composition layer comprising (i) insulative partition walls and (ii) an electrochromic composition including a supporting electrolyte, a polar solvent, and a leuco dye, and wherein the device displays a selected pixel by applying a voltage of a first potential difference, and applies the voltage of a second potential difference so as not to cause any energization.