Abstract: Disclosed is an electrochromic display device, including, a first substrate, first electrodes provided on an upper surface of the first substrate, a second substrate provided to be opposed to the first substrate above the first substrate, the second substrate being formed of a transparent material, second electrodes provided on an undersurface of the second substrate, at least a part of the second electrodes being formed of a transparent electrode material, and an electrochromic composition layer provided between the first substrate and the second substrate. The electrochromic composition layer contains an electrochromic composition including a supporting electrolyte, a polar solvent, a leuco dye, a hydroquinone derivative and/or a catechol derivative, a ferrocene derivative, and a compound having a carbonyl group.

Abstract: Disclosed is an electrochromic display device comprising: a first and a second substrates; a first and a second electrodes; and an electrochromic composition layer, wherein the device is of a passive matrix drive where the a display and an erasion are performed by an energization in reverse directions between the electrodes, the first and the second electrodes respectively comprise a plurality of electrodes, a pixel is formed where the electrodes are in a grade separated crossing, and the display is performed by voltage application processing where: (i) the first electrode is set as negative, and the second electrode is set as positive, to apply a voltage of a first potential difference, immediately followed by (ii) the first electrode being set as positive, and the second electrode being set as negative, to apply a voltage of a second potential difference equal to or more than the first potential difference.

Abstract: Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A PMOS transistor is disposed on the first doped region layer. An NMOS transistor is disposed on the second doped region. A first capping layer is disposed covering the NMOS transistor over the first region. A second capping layer is disposed covering the PMOS transistor over the first region. The thickness of the first capping layer is different from the thickness of the second capping layer, thereby different stress is induced on the PMOS transistor and the NMOS transistor respectively. The PMOS transistor and the NMOS transistor over the second region are silicided.

Abstract: Disclosed is an electrochromic display device comprising: a first substrate; a first electrode; a second substrate; a second electrode; and an electrochromic composition layer, wherein the device is of a passive matrix drive where the device performs a display by an energization between the electrodes, and performs a erasion of the display, wherein the first electrode comprises electrodes, the second electrode comprises a plurality of transparent display electrodes, a pixel is formed where the electrodes are in a grade separated crossing, at least a surface of the electrodes is respectively oxidized, the electrochromic composition layer comprising (i) insulative partition walls and (ii) an electrochromic composition including a supporting electrolyte, a polar solvent, and a leuco dye, and wherein the device displays a selected pixel by applying a voltage of a first potential difference, and applies the voltage of a second potential difference so as not to cause any energization.

Abstract: Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A PMOS transistor is disposed on the first doped region layer. An NMOS transistor is disposed on the second doped region. A first capping layer is disposed covering the NMOS transistor over the first region. A second capping layer is disposed covering the PMOS transistor over the first region. The thickness of the first capping layer is different from the thickness of the second capping layer, thereby different stress is induced on the PMOS transistor and the NMOS transistor respectively. The PMOS transistor and the NMOS transistor over the second region are silicided.

Abstract: The invention describes a method to facilitate the use of low-sensitivity monitoring equipment for detecting and monitoring defects on the surface of semiconductor wafers. The method includes the use of a hydrofluoric acid solution for increasing the dimensions of a defect and the application of a thin-film layer of a metal, such as titanium, for improving the appearance of the defect such that the defect dimensions increase to above 0.1 nanometer, the detection threshold for economical low-sensitivity monitoring equipment.

Abstract: A method for fabricating a capacitor in a semiconductor device that includes providing a semiconductor substrate, forming at least one shallow trench isolation structure in the semiconductor substrate, forming a tunnel oxide layer over the semiconductor substrate, depositing a first polysilicon layer over the tunnel oxide layer, depositing a nitride layer over the first polysilicon layer, depositing a first photoresist over the nitride layer, patterning and defining the first photoresist layer to expose at least a portion of the nitride layer, etching the exposed portion of the nitride layer and the first polysilicon layer underneath the exposed portion of the nitride layer to expose at least a portion of the tunnel oxide layer, removing the patterned and defined photoresist layer, forming a second oxide layer over at least the exposed portion of the tunnel oxide layer, providing a second photoresist layer over the second oxide layer, providing an etchback process to remove a portion of the second photoresist

Abstract: The invention describes a method to facilitate the use of low-sensitivity monitoring equipment for detecting and monitoring defects on the surface of semiconductor wafers. The method includes the use of a hydrofluoric acid solution for increasing the dimensions of a defect and the application of a thin-film layer of a metal, such as titanium, for improving the appearance of the defect such that the defect dimensions increase to above 0.1 nanometer, the detection threshold for economical low-sensitivity monitoring equipment.

Abstract: A method for fabricating a capacitor in a semiconductor device that includes providing a semiconductor substrate, forming at least one shallow trench isolation structure in the semiconductor substrate, forming a tunnel oxide layer over the semiconductor substrate, depositing a first polysilicon layer over the tunnel oxide layer, depositing a nitride layer over the first polysilicon layer, depositing a first photoresist over the nitride layer, patterning and defining the first photoresist layer to expose at least a portion of the nitride layer, etching the exposed portion of the nitride layer and the first polysilicon layer underneath the exposed portion of the nitride layer to expose at least a portion of the tunnel oxide layer, removing the patterned and defined photoresist layer, forming a second oxide layer over at least the exposed portion of the tunnel oxide layer, providing a second photoresist layer over the second oxide layer, providing an etchback process to remove a portion of the second photoresist

Abstract: A gingival retraction material is prepared using fibrillated fibers to improve viscosity and combining taste-modifying agent, color agent, and kaolin filler to form a paste-like structure having the viscosity ranging from 31.0×106 cP to 71.0×106 cP. The gingival material is injectable into the patient's gingival sulcus to provide a physical active force that widens the patient's gingival sulcus by means of the material viscosity and also to control gingival tissue fluid and hemostasis so as to keep the gingival sulcus dry for further mold impressions.

Abstract: Alignment structures in gaps between patterned features, such as polysilicon wordlines or metal contacts, have a selective effect on various processes to promote self-alignment. The various processes include ion implants for code programming, formation of via cuts, and the polycide process of forming composite layered gates. The alignment structures improve these processes by having a selective effect during etching, deposition, and ion implants. Thus, in one example, to prepare a ROM array for code programming using the ion implantation process, the alignment structures or ion barrier walls are formed between the plurality of wordlines. These ion barrier walls, typically silicon nitride or silicon dioxide, have a height above the substrate that is greater than the height of the wordlines. When viewed from a direction orthogonal to the substrate, only the ion barrier walls and wordlines are visible.

Abstract: A high performance and high density integrated circuit includes interbank bitlines and a bank select structure which improve the vertical pitch of the integrated circuit layout and provide the selective access of data stored in the memory cells. The bank select structures includes bank select transistors which are located and oriented adjacent metal-to-diffusion region contacts such that vertical pitch of the layout is improved, thus promoting a higher density memory array. The bank select transistor is also formed such that conductivity is increased and impedance decreased due to a relatively wide channel width. On the substrate, a plurality of bitlines, including interbank bitlines and intrabank bitlines, and a plurality of wordlines are provided to form memory cells. In bank BK.sub.N, each interbank bitline extends into either bank BK.sub.N-1 or BK.sub.N+1 adjacent to bank BK.sub.N. For the selection of a cell or plurality of cells in bank BK.sub.N, bank BK.sub.