Abstract: A level shifter includes a cross-coupled transistor pair, first through third biased transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first biased transistor pair is controlled by a first reference voltage. The second biased transistor pair is controlled by a pair of differential control voltages. The third biased transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second biased transistor pair.

Abstract: A liquid crystal display includes a display panel and a driving unit. The display panel includes a plurality of resetting sections, which correspond to display a plurality of screens, respectively. There is a first voltage difference between a corresponding one of the column voltages and a corresponding one of the row voltages of one of the resetting sections, and there is a second voltage difference between a corresponding one of the column voltages and a corresponding one of the row voltages of another of the resetting sections. The second voltage difference reaching a second maximum voltage difference value is after the first voltage difference reaching a first maximum voltage difference value by a delay time, so as to clear the screens.

Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode and a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. A top electrode is disposed on the MTJ. The top electrode includes two or more tiers wherein each tier successively includes a smaller footprint.

Abstract: The present invention relates to a cholesteric liquid crystal display, a micro processing unit, and a method for hybrid driving. The cholesteric liquid crystal display comprises a display panel and a micro processing unit. First, a grayscale threshold value needs to be set in advance. The micro processing unit will change the grayscale value of the display unit exceeding the grayscale threshold value to the new grayscale value displayed by the bright state color, and display the image by the DDS driving mode. Then the micro processing unit drives the display image in the PWM drive mode, which can greatly improve the color level and contrast display effect of the image.

Abstract: A cholesteric liquid crystal (ChLC) display and driving method thereof are provided. The ChLC display has a driving circuit for providing voltage on a scan line and a data line so as to drive a pixel. The driving circuit provides a first voltage and a second voltage to the data and the scan lines during a first time period, a third voltage to the data line and/or a fourth voltage to the scan line during a second time period, a fifth voltage and a sixth voltage to the data and the scan lines during a third time period. The first and sixth voltages are high levels, the second and fifth voltages are low levels, the levels of the third and fourth voltages are between the high and low levels.

Abstract: A button structure includes a switch, a shell, an elastic member, a button and at least one adjustable limiting member. The elastic member includes a fixing portion, a compressive portion and an elastic portion. The fixing portion is connected to the shell. The compressive portion is configured to abut against the switch. The elastic portion is connected between the fixing portion and the compressive portion. The elastic portion is suitable for deformation. The button is connected to the compressive portion, and the compressive portion is located between the button and the switch. The adjustable limiting member is disposed on the button, and is configured to abut against the elastic portion. The adjustable limiting member adjustably protrudes for a length toward the elastic portion relative to the button.

Abstract: A semiconductor device includes a bottom electrode via, a top electrode via over the bottom electrode via, a memory cell between the bottom electrode via and the top electrode via, a first dielectric layer over the memory cell, and a second dielectric layer over the first dielectric layer, and a via structure separated from the memory cell. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell, and a height of the top electrode via. The first dielectric layer partially surrounds a first portion of the via structure, and the second dielectric layer partially surrounds a second portion of the via structure. A height of the second portion of the via structure is greater than a height of the first portion of the via structure.

Abstract: A fuse structure including a first conductive line and a second conductive line, a first metal pillar extending vertically from a top surface of the first conductive line and a second metal pillar extending vertically from a top surface of the second conductive line, a conductive link electrically connecting a top surface of the first metal pillar with a top surface of the second metal pillar, where both the first conductive line and the second conductive line are a different material than both the first metal pillar and the second metal pillar, and where both the first metal pillar and the second metal pillar are a different metal than the conductive link.

Abstract: A display device includes a housing. The housing includes a main body, a first fixed end, a second fixed end, a third fixed end, a fourth fixed end, and an opening area. The opening area is disposed at a lower half portion of the main body. The opening area has a first opening, a second opening, and a third opening. The first opening has an axis extending along a first direction substantially perpendicular to a bottom side of the main body. The second opening is disposed on a first side of the first opening and has an axis extending along a second direction having a first angle with respect to the first direction. The third opening is disposed on a second side of the first opening opposite to the first side and has an axis along a third direction having a second angle with respect to the first direction.

Abstract: A cholesteric liquid crystal display device includes a first substrate, a solar cell, a shielding layer, a first electrode layer, a cholesteric liquid crystal layer, a second electrode layer and a second substrate stacked sequentially from bottom to top. The solar cell includes a metal wiring pattern layer. The shielding layer corresponds to the upper side of the metal wiring pattern layer, and is used to reduce the reflection of light from the metal circuit pattern layer. In this way, the cholesteric liquid crystal display device replaces the traditional black absorbing layer with the black material of the solar cell, which can not only absorb light, but also display the image with self-sustaining power. The cholesteric liquid crystal display device shields the arrangement of the metal wiring pattern layer through the shielding layer, which can ensure the image quality of the display panel.

Abstract: A cholesteric liquid crystal display device and a control method for reducing inrush current when clearing the screen. The cholesteric liquid crystal display device includes a cholesteric liquid crystal display panel and a liquid crystal drive unit. The cholesteric liquid crystal display panel has a plurality of pixel matrix. After the liquid crystal drive unit receives a data latch enable signal, it applies a reset voltage to the plurality of pixel matrix to clear the screen displayed on the cholesteric liquid crystal display panel. The input time of the data latch enable signal received by the liquid crystal driving unit is different, and the corresponding signal time portion is shifted with each other.

Abstract: A self-powered cholesteric liquid crystal display (ChLCD) device and a method for tracking maximum power are disclosed. The ChLCD device includes a solar cell module, electrical energy for charging, an energy storage device, a charging unit, and a ChLCD module. The method of tracking the maximum power is: supply electrical energy for charging to the charging unit, sense the ambient temperature, and capture the sensed ambient temperature, correspond its value to the voltage value in the comparison data, and adjust the reference driving voltage with a resistor divider, and then electrically charging to the charging unit by the reference driving voltage, so that the charging unit can capture the maximum power of the electrical energy from the solar cell module, and then store the electrical energy in the energy storage device, to refresh the display screen of the ChLCD module and the ChLCD device can effectively utilize electricity.

Abstract: A cholesteric liquid crystal display device and a driving method for improving non-uniform image quality of the cholesteric liquid crystal display device. The cholesteric liquid crystal display device includes a cholesteric liquid crystal display panel and a liquid crystal drive unit. The cholesteric liquid crystal display panel is composed of multiple row circuit structures and multiple column circuit structures. The liquid crystal driving unit sequentially outputs column driving voltages to a plurality of column circuit structures in a scanning manner. After scanning the multiple column circuit structures, the liquid crystal driving unit applies an unselected voltage to the multiple column circuit structures together with more than 18 times the scanning unit time course, so as to make the brightness of the overall picture more uniform.

Abstract: A cholesteric liquid crystal display device includes a first substrate, a second substrate, a third substrate, a first cholesteric liquid crystal layer, a second cholesteric liquid crystal layer, a first common electrode pattern layer, a second common electrode pattern layer, and a first TFT circuit pattern layer and the second TFT circuit pattern layer. The first cholesteric liquid crystal layer is disposed between the first substrate and the second substrate. The second cholesteric liquid crystal layer is disposed between the second substrate and the third substrate. The first common electrode pattern layer is disposed on the first substrate. The second common electrode pattern layer is disposed on the third substrate. The first TFT circuit pattern layer and the second TFT circuit pattern layer are respectively disposed on two opposite surfaces of the second substrate. The first TFT circuit pattern layer and the second TFT circuit pattern layer are arranged correspondingly.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.

Abstract: A cholesterol liquid crystal display device includes a liquid crystal display panel and a liquid crystal driving unit. The liquid crystal display panel has a plurality of pixels. The liquid crystal driving unit applies row driving voltages and column driving voltages to a designated pixel according to the input signal. After the input signal is transmitted, the liquid crystal driving unit activates the power-down signal within a certain period of time to reduce the row driving voltage and the column driving voltage applied to the specified pixel. Thereby, the crosstalk phenomenon on the cholesteric liquid crystal display device can be improved.

Abstract: The present invention relates to a driving method of a cholesteric liquid crystal display. It includes the steps in the following: driving each scan line by a dynamic driving scheme (DDS) including an Evolution phase; refreshing a frame of the cholesteric liquid crystal display by a full refresh mode, each scan line driven N times during the Evolution phase in the full refresh mode; and refreshing a part of the frame by a partial-refresh mode, each scan line driven M times in the Evolution phase in the partial-refresh mode, wherein M is greater than N.

Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.

Abstract: An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.

Abstract: A semiconductor device includes a bottom electrode via, a top electrode via over the bottom electrode via, a memory cell between the bottom electrode via and the top electrode via, a first dielectric layer over the memory cell, and a second dielectric layer over the first dielectric layer, and a via structure separated from the memory cell. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell, and a height of the top electrode via. The first dielectric layer partially surrounds a first portion of the via structure, and the second dielectric layer partially surrounds a second portion of the via structure. A height of the second portion of the via structure is greater than a height of the first portion of the via structure.