Abstract: A network attack processing method and a processing apparatus are disclosed herein. The method may include; after determining an attacked object, searching for a recorded attack event related to the attacked object to determine a controlled host in an attack network; searching for a recorded control event related to the controlled host to determine a controlling host in the attack network; and determining a detected host which performs similar communication with the multiple controlling hosts as an attack manipulator. Accordingly, embodiments for a processing apparatus adapted to perform the methods are disclosed herein.

Abstract: Disclosed is a flood attack detection method, wherein the total number of keywords of a source packet is acquired, and the number of feature parameters corresponding to the source packet is acquired. A ratio of the number of feature parameters to the total number of keywords is compared with a preset threshold, and if the ratio is greater than or equal to the preset threshold, it is determined that a flood attack occurs.

Abstract: A weak battery warning circuit includes a warning circuit for generating an alarm; a battery having a cathode connected to ground; and a controlling circuit comprising a transistor, the transistor having an emitter for receiving an input voltage, a base connected to an anode of the battery via a base resistor, and a collector connected to the warning circuit and also connected to ground via a collector resistor. When the voltage of the battery reduces to a predetermined value, the controlling circuit controls the warning circuit to alarm.

Abstract: A supply voltage switching circuit for a computer includes a chipset, a first transistor and a second transistor. The chipset includes a first MOSFET and a second MOSFET. A 5V system voltage and a 5V standby voltage are respectively inputted to sources of the first MOSFET and the second MOSFET. Gates of the first MOSFET and the second MOSFET are respectively coupled to collectors of the first transistor and the second transistor. Emitters of the first transistor and the second transistor are coupled to a first terminal for receiving a control signal. A 1.8V standby voltage is separately inputted to bases of the first transistor and the second transistor. A 12V system voltage and the 5V standby voltage are respectively inputted to collectors of the first transistor and the second transistor. A second terminal is connected between the drain of the first MOSFET and the drain of the second MOSFET.

Abstract: A heat dissipation assembly for dissipating heat generated by an electronic component includes a heat sink contacting the electronic component, a pair of retaining members fixed on two lateral sides of a top portion of the heat sink, a pair of arms pivotably secured to the retaining members, and an operating member pivotably attached to the retaining members. The operating member has two cams for interacting with the retaining member and the heat sink. When the operating member is rotated from a vertical orientation to a horizontal orientation, the arms are driven by the operating member to rotate towards the heat sink to engage with barbs of a retention module. Furthermore, the arms are also activated to move upwardly so they can tightly engage with the barbs, thereby securing the heat sink to the electronic component.

Abstract: A heat sink assembly for removing heat from two heat generating-components mounted on a printed circuit board, includes a first heat sink, a second heat sink, a plurality of poles each having a head at a top end and a double-layer spring. The first heat sink includes a base and a plurality of fins arranged on the base. The second heat sink has a first shoulder extending from a lateral side thereof. The first shoulder is disposed on the base. The double-layer spring includes an outer spring and an inner spring having a top end connected to a top end of the outer spring. One of the poles wearing the double-layer spring extends through the first shoulder and the base. The outer spring is compressed between the head of the pole and the first shoulder. The inner spring is compressed between the head of the pole and the base.

Abstract: A heat sink assembly for removing heat from a plurality arrays of heat generating-components mounted on a printed circuit board includes a fist and a second heat sink, a plurality of fastening assemblies. Each of the first and second heat sinks comprises an elongated base and a plurality of fins mounted on the base. The base extends beyond the fins at two lateral sides of the fins to form a first shoulder and a second shoulder located above the first shoulder in a manner such that the second shoulder of the first heat sink is superposed on the first shoulder of the second heat sink. The fastener assembly extends through the superposed first and second shoulders of the first and second heat sinks to assemble the first and second heat sinks on the printed circuit board.

Abstract: A heat dissipation assembly for dissipating heat generated by an electronic component includes a heat sink contacting the electronic component, a pair of retaining members fixed on two lateral sides of a top portion of the heat sink, a pair of arms pivotably secured to the retaining members, and an operating member pivotably attached to the retaining members. The operating member has two cams for interacting with the retaining member and the heat sink. When the operating member is rotated from a vertical orientation to a horizontal orientation, the arms are driven by the operating member to rotate towards the heat sink to engage with barbs of a retention module. Furthermore, the arms are also activated to move upwardly so they can tightly engage with the barbs, thereby securing the heat sink to the electronic component.

Abstract: A memory voltage generating circuit includes a first control module, a core circuit, and a second control module. The core circuit includes a regulation amplifier, a first MOSFET, a second MOSFET, and a switch. An output terminal and an inverting input terminal of the regulation amplifier are both connected to an output terminal of the core circuit. A non-inverting input terminal of the regulation amplifier is coupled to the second control module. The non-inverting input terminal of the regulation amplifier is also connected to a referenced voltage via one resistor and is grounded via another resistor. A source of the first MOSFET is coupled to the inverting input terminal of the regulation amplifier. A gate of the first MOSFET is connected to the output terminal of the regulation amplifier. Drains of the first MOSFET and the second MOSFET are coupled to an input voltage via the switch. A source of the second MOSFET is connected to another input voltage.

Abstract: A power good signal generating circuit includes an NPN transistor, a first resistor, a second resistor, a third resistor, a first power source, and a second power source. The first resistor is connected between a base of the transistor and the first power source. The second resistor is connected between a collector of the transistor and the second power source. The third resistor is connected between an emitter of the transistor and ground. The collector is connected to an output for sending a PG signal and the emitter is connected to an input for receiving a control signal P.

Abstract: A heat dissipation device includes a heat sink (10) and a fan (30) mounted on the heat sink via a pair of fan holders (20) and clips (40). The fan holders each have a supporting plate (24) attached on the heat sink and a sleeve (26) connected to the supporting plate and spaced from the supporting plate. The fan has upper and lower flanges (32, 34). The lower flange is sandwiched between the sleeve and the supporting plate. The clips each include a shaft (42) extending through the sleeve, a spring (44) mounted around and received in sleeve, and a handle (46) pivotably mounted on the shaft and movable between unlocked and locked positions. When the handle is positioned at the locked position, the shaft is inserted in the lower flange of the fan to thereby secure the fan on the heat sink.

Abstract: A linear voltage regulator provides a regulated load voltage to a load. In a preferred embodiment, the linear voltage regulator includes: a regulating circuit for receiving an input voltage and providing an output voltage to a load, the regulating circuit being driven by a driving voltage; and two resistors connected to each other in series receiving the output voltage and providing an adjusting current to the regulating circuit. The linear voltage regulator is capable of providing a greater current to the load, and having a wide range of input voltages.

Abstract: A system for designing a delayer emulation model (1) includes a delayer emulation model generating apparatus (2). The delay emulation model generating apparatus includes: a delay circuit defining module (20) for defining delay parameters of a delay circuit, and generating the delay circuit; a delay signal setting module (21) for setting a delay interval for the transition from a high voltage to a low voltage and a delay interval for the transition from a low voltage to a high voltage of an input delay signal; a voltage regulation circuit defining module (22) for defining voltage parameters of a voltage regulation circuit, and generating the voltage regulation circuit; a voltage regulating module (23) for regulating a voltage of the input delay signal from the delay circuit according to requirements of an output delay signal; and a model calling module (24) for generating the delayer emulation model by means of calling the delay circuit and the voltage regulation circuit.

Abstract: A control circuit for command signals of a clock generator includes a power supply end, an output end, a control end, a diode, a first resistor and a second resistor. The first resistor, the diode, and the second resistor are connected in series between the power supply end and the ground. The diode has an anode connected to the first resistor and a cathode connected to the second resistor. The control end is connected to a node between the diode and the second resistor; the output end is connected to a node between the diode and the first resistor. The output end outputs the command signals to the clock generator.

Abstract: A supply voltage switching circuit for a computer includes a chipset, a first transistor, a second transistor, and a third transistor. The chipset includes a first MOSFET and a second MOSFET. A 5V system voltage and a 5V standby voltage are respectively inputted to sources of the first MOSFET and the second MOSFET. Gates of the first MOSFET and the second MOSFET are respectively coupled to collectors of the second transistor and the third transistor. A base of the first transistor is coupled to a terminal for receiving a control signal from the computer. The 5V standby voltage is inputted to a collector of the first transistor. Bases of the second transistor and the third transistor are coupled to the collector of the first transistor. A 12V system voltage and the 5V standby voltage are respectively inputted to collectors of the second transistor and the third transistor.

Abstract: A reflective light imaging system for use in high-throughput screening of samples disposed in multiple-well plates. The system can include a set of mirrors and lenses. The first mirror has a central aperture through which light from the object passes. The first mirror has a concave reflective surface that faces the image plane. The next element is a second mirror with a convex reflective surface. The system can include an aberration corrective system positioned between the second mirror and the image plane, and an optical sensor near the image plane. Light from an object passes through the central aperture of the first mirror and is reflected off the convex surface of the second mirror. The light then strikes the reflective surface of the first mirror. The light from the first mirror is then collected by the aberration correction system and transmitted toward the image plane.

Abstract: A linear voltage regulator provides a selectable output voltage to a load. The linear voltage regulator includes: a regulating circuit including an input terminal for receiving an input voltage, an output terminal for providing an output voltage to a load, and an adjusting terminal; a first resistor and a second resistor connected between the output terminal and ground for receiving the output voltage; and a voltage sampling control circuit electrically connected to a node between the first resistor and the second resistor for receiving logic signals from a controlling chip, and generating a reference current to the adjusting terminal of the regulating circuit to provide the selectable output voltage.

Abstract: A linear voltage regulator provides a selectable output voltage to a load. The linear voltage regulator includes: a regulating circuit including an input terminal for receiving an input voltage, an output terminal for providing an output voltage to a load, and an adjusting terminal; a first resistor and a second resistor connected between the output terminal and ground for receiving the output voltage; and a voltage sampling control circuit electrically connected to a node between the first resistor and the second resistor for receiving logic signals from a controlling chip, and generating a reference current to the adjusting terminal of the regulating circuit to provide the selectable output voltage.

Abstract: A linear voltage regulator is provided for providing an output voltage to a load. In a preferred embodiment, the linear voltage regulator comprises: an operational amplifier receiving a regulated voltage, and a first voltage reference, and providing a driving voltage; a first regulating transistor driven by the driving voltage, the regulating transistor receiving a system voltage, and providing the regulated voltage; a second regulating transistor receiving the regulated voltage, and providing an output voltage, the second regulating transistor controlled by a controlling voltage; a resistive voltage divider receiving the output voltage, and providing a second voltage reference; and a three-terminal adjustable shunt regulator receiving the second voltage reference, and providing the controlling voltage to the second regulating transistor.

Abstract: A memory voltage generating circuit includes a first control module, a core circuit, and a second control module. The core circuit includes a regulation amplifier, a first MOSFET, a second MOSFET, and a switch. An output terminal and an inverting input terminal of the regulation amplifier are both connected to an output terminal of the core circuit. A non-inverting input terminal of the regulation amplifier is coupled to the second control module. The non-inverting input terminal of the regulation amplifier is also connected to a referenced voltage via one resistor and is grounded via another resistor. A source of the first MOSFET is coupled to the inverting input terminal of the regulation amplifier. A gate of the first MOSFET is connected to the output terminal of the regulation amplifier. Drains of the first MOSFET and the second MOSFET are coupled to an input voltage via the switch. A source of the second MOSFET is connected to another input voltage.