Abstract: A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.

Abstract: A communication system includes a demodulator configured to demodulate an amplified modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal. The first signal is based on the first carrier signal and the amplified modulated signal. The filter has a gain adjusted based on a set of control signals. The gain adjusting circuit is coupled to the filter, and configured to generate the set of control signals based on at least a voltage of the filtered first signal or a voltage of a second signal. The gain adjusting circuit includes a first peak detector configured to output a peak value of the voltage of the second signal. The voltage of the second signal includes a voltage of the first signal or a voltage of a reference signal.

Abstract: A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.

Abstract: A modular system for muffler production and assembly allows various muffler designs to be produced from a common set of components. In particular, modular stamped muffler housing components, including two endcap designs and an intermediate body component design, can be assembled in various ways to produce muffler shells of varying length and configuration, while also ensuring high performance of the finished product. Additional components, such as crossover tubes, baffles and manifold pipes, may be integrated into a particular muffler design upon final assembly.

Abstract: Systems and methods for die-to-die communication are provided. A first transceiver disposed on a first die includes a transmission section configured to modulate first data onto a carrier signal having a first frequency. The first transceiver includes a reception section configured to receive signals from a transmission line. The reception section includes a filter configured to pass frequencies within a first passband that includes a second frequency. The first frequency is outside of the first passband. A second transceiver is disposed on a second die and is configured to communicate with the first transceiver via the transmission line. The second transceiver includes a transmission section configured to modulate second data onto a carrier signal having the second frequency. The second transceiver includes a reception section including a filter configured to pass frequencies within a second passband that includes the first frequency. The second frequency is outside of the second passband.

Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.

Abstract: A receiver circuit includes a plurality of receivers, each of the receivers being associated with a carrier of a plurality of carriers, and a decoupler configured to receive a transmission signal from a transmission channel and output a plurality of divided transmission signals to the plurality of receivers. An equalizer is configured to modify either the transmission signal or one of the divided transmission signals.

Abstract: A device, a circuit and a method are disclosed herein. The device includes a data receiving circuit and an oscillating signal generator. The data receiving circuit is configured to output a first output signal, a second output signal, and a phase error signal according to an oscillating signal and a modulated signal, in which the phase error signal indicates a phase difference between the oscillating signal and the modulated signal. The oscillating signal generator is configured to delay a phase of a first reference signal according to the phase error signal, to generate the oscillating signal.

Abstract: A circuit includes a transmitter associated with a carrier of a radio frequency interconnect, a transmission channel communicatively coupled with the transmitter, and a receiver communicatively coupled with the transmission channel, the receiver also being associated with the carrier of the radio frequency interconnect. A combiner on a transmitter-side of the transmission channel is coupled between the transmitter and the transmission channel, and a decoupler on a receiver-side of the transmission channel is coupled between the receiver and the transmission channel. A channel loss compensation circuit is communicatively coupled between the transmitter and the receiver.

Abstract: A communication system includes a first amplifier configured to output an amplified modulated signal, and a demodulator coupled to the first amplifier. The demodulator is configured to demodulate the amplified modulated signal responsive to a first carrier signal. The demodulator includes a filter and a bandwidth adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal and a set of control signals. The filter has a bandwidth adjusted based on the set of control signals. The bandwidth adjusting circuit is coupled to the filter, and is configured to generate the set of control signals based on a frequency of the filtered first signal and a frequency of the first signal. The bandwidth adjusting circuit includes a frequency detector configured to generate a second signal based on the frequency of the filtered first signal and the frequency of the first signal.

Abstract: A radio frequency interconnect (RFI) includes a transmitter side connected to a first end of a channel, a receiver side connected to a second end of the channel opposite the first end and a calibration system. The receiver side includes at least one of the following configurations: (a) at least one gain control amplifier (GCA) or at least one analog to digital converter (ADC). The calibration system is configured to transmit a predetermined data set through the channel, receive an output from the at least one ADC or the at least one GCA, and calibrate the at least one ADC or the at least one GCA based on a measured data set. The output includes the measured data set based on the predetermined data set transmitted through channel.

Abstract: The present disclosure, in some embodiments, relates to an integrated antenna structure. The structure includes an excitable element and a first ground plane. The first ground plane is disposed between a first surface of a semiconductor substrate and the excitable element. A first line that is normal to the first surface of the semiconductor substrate extends through both the first ground plane and the excitable element. A second ground plane is separated from the first ground plane by the semiconductor substrate. The second ground plane is electrically coupled to the first ground plane.

Abstract: Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.

Abstract: A communication system includes a demodulator configured to demodulate an amplified modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal. The first signal is based on the first carrier signal and the amplified modulated signal. The filter has a gain adjusted based on a set of control signals. The gain adjusting circuit is coupled to the filter, and configured to generate the set of control signals based on at least a voltage of the filtered first signal or a voltage of a second signal. The gain adjusting circuit includes a first peak detector configured to output a peak value of the voltage of the second signal. The voltage of the second signal includes a voltage of the first signal or a voltage of a reference signal.

Abstract: A phase locked loop (PLL) for a carrier generator includes a front-end circuit that receives a frequency reference signal and generates a control signal based on the frequency reference signal and a feedback signal. A demultiplexer selectively outputs the control signal to a plurality of tuning arrangements. The plurality of tuning arrangements includes a first tuning arrangement that generates a first carrier signal based on the control signal and a second tuning arrangement that generates a second carrier signal based on the control signal. A multiplexer outputs the feedback signal based on the first carrier signal and the second carrier signal.

Abstract: A device, a circuit and a method are disclosed herein. The device includes a data receiving circuit and an oscillating signal generator. The data receiving circuit is configured to output a first output signal, a second output signal, and a phase error signal according to an oscillating signal and a modulated signal, in which the phase error signal indicates a phase difference between the oscillating signal and the modulated signal. The oscillating signal generator is configured to delay a phase of a first reference signal according to the phase error signal, to generate the oscillating signal.

Abstract: A radio frequency interconnect includes a transmitter coupled with an input end of a transmission line, and a receiver coupled with an output end of the transmission line. The transmitter includes a first carrier generator configured to generate a clock recovery signal based on a carrier signal, to output a reference clock signal, and to transmit the clock recovery signal to the receiver. The transmitter also includes a modulator configured to modulate a data packet based on the carrier signal. The transmitter also includes a preamble generator configured to generate and add a preamble to data to generate the data packet. The preamble includes a data sequence associated with the reference clock signal. The transmitter further includes a transmitter output configured to transmit the modulated data packet to the receiver by the transmission line.

Abstract: A communication system includes a first amplifier configured to output an amplified modulated signal, and a demodulator coupled to the first amplifier. The demodulator is configured to demodulate the amplified modulated signal responsive to a first carrier signal. The demodulator includes a filter and a bandwidth adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal and a set of control signals. The filter has a bandwidth adjusted based on the set of control signals. The bandwidth adjusting circuit is coupled to the filter, and is configured to generate the set of control signals based on a frequency of the filtered first signal and a frequency of the first signal. The bandwidth adjusting circuit includes a frequency detector configured to generate a second signal based on the frequency of the filtered first signal and the frequency of the first signal.

Abstract: A communication system includes a demodulator configured to demodulate a modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal. The first signal is a product of the first carrier signal and the modulated signal. The filter has a gain adjusted based on a set of control signals. The gain adjusting circuit is coupled to the filter, and is configured to generate the set of control signals based on at least a voltage of the filtered first signal. The gain adjusting circuit includes a first peak detector coupled to the filter. The first peak detector is configured to output a peak value of the voltage of the filtered first signal.

Abstract: A digital code recovery circuit includes a data transmitter that outputs either input data or a preamble code as transmitter data. A radio frequency interconnect (RFI) transmitter modulates carrier signals based on the transmitter data and transmits the modulated carrier signals over a channel to an RFI receiver that demodulates the carrier signals to obtain recovered transmitter data. A calibration storage device stores preamble data and a calibration circuit receives the recovered transmitter data. If the recovered transmitter data originated from the preamble code, the calibration circuit determines a set of digital calibration adjustments from the recovered transmitter data and the preamble data. If the recovered transmitter data originated from the input data, the calibration circuit applies the set of digital calibration adjustments to the recovered transmitter data to obtain adjusted digital code and outputs the adjusted digital code.