Abstract: A depletion type vertical discrete NMOS device includes: an N-type epitaxial layer formed on an N-type substrate, wherein the N-type epitaxial layer has a top surface and a bottom surface opposite to each other; a P-type well formed in the N-type epitaxial layer; a gate formed outside and connected with the N-type epitaxial layer; an N-type source formed in the N-type epitaxial layer and in contact with the P-type well; an N-type drain including a part of the N-type substrate, which is formed outside and under the N-type epitaxial layer; and an N-type region formed and connected between the P-type well and the gate, which provides a channel, such that the N-type source and the N-type drain are electrically connected with each other during conduction operation, whereas, the N-type source and the N-type drain are electrically disconnected from each other during non-conduction operation.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

Abstract: A junction field effect transistor device includes a substrate, a well region, a first top layer, a plurality of source/drain regions, a first isolation structure, a gate, and a plurality of first well slots. The substrate has a first conductivity type. The well region is embedded in the substrate. The well region has a second conductivity type. The first top layer is embedded in the well region. The first top layer has the first conductivity type. The source/drain regions are disposed on a top surface of the well region. The first isolation structure is adjacent to one of the source/drain regions. The gate is disposed on a top surface of the first top layer. The first well slots are disposed below the gate. A second-conductivity-type dopant concentration of the first well slots is lower than a second-conductivity-type dopant concentration of the well region.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body contact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A native NMOS device includes: a P-type epitaxial layer, a first and a second insulation region, a first P-type well, a second P-type well, a gate, an N-type source, and an N-type drain. The P-type epitaxial layer has a first concentration of P-type doped impurities. The first P-type well completely encompasses and is in contact with a lower surface of the N-type source. The second P-type well completely encompasses and is in contact with a lower surface of the N-type drain. Each of the first P-type well and the second P-type well has a second concentration of P-type doped impurities, and the second concentration of P-type doped impurities is higher than the first concentration of P-type doped impurities. The second concentration of P-type doped impurities is sufficient for preventing a leakage current from flowing between the N-type drain and the P-type substrate while the native NMOS device is in operation.

Abstract: A semiconductor device with a pad structure resistant to plasma damage includes: a main pad portion including main conductor units and main via units; a sub-pad portion including sub-conductor units and sub-via units; a pad bonding unit in direct contact with and in connection with a top main conductor unit, wherein the top main conductor unit is the main conductor unit formed in a top metal layer; and a bridge pad unit in direct contact with a top sub-conductor unit, wherein the top sub-conductor unit is the sub-conductor unit formed in the top metal layer. The bridge pad unit is in direct contact with the pad bonding unit. The main pad portion and sub-pad portion are located below the pad bonding unit and bridge pad unit respectively, and the main pad portion and the sub-pad portion are not in direct connection with each other.

Abstract: A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/° C.

Abstract: A high voltage complementary metal oxide semiconductor (CMOS) device includes: a semiconductor layer, plural insulation regions, a first N-type high voltage well and a second N-type high voltage well, which are formed by one same ion implantation process, a first P-type high voltage well and a second P-type high voltage well, which are formed by one same ion implantation process, a first drift oxide region and a second oxide region, which are formed by one same etching process by etching a drift oxide layer; a first gate and a second gate, which are formed by one same etching process by etching a polysilicon layer, an N-type source and an N-type drain, and a P-type source and a P-type drain.

Abstract: An integrated structure of CMOS devices includes: a semiconductor layer, insulation regions, a first high voltage P-type well and a second high voltage P-type well, a first high voltage N-type well and a second high voltage N-type well, a first low voltage P-type well and a second low voltage P-type well, a first low voltage N-type well and a second low voltage N-type well, and eight gates. A CMOS device having an ultra high threshold voltage is formed in ultra high threshold device region; a CMOS device having a high threshold voltage is formed in high threshold device region; a CMOS device having a middle threshold voltage is formed in the middle threshold device region; and a CMOS device having a low threshold voltage is formed in the low threshold device region.

Abstract: An NMOS half-bridge power device includes: a semiconductor layer, a plurality of insulation regions, a first N-type high voltage well and a second N-type high voltage well, which are formed by one same ion implantation process, a first P-type high voltage well and a second P-type high voltage well, which are formed by one same ion implantation process, a first drift oxide region and a second drift oxide region, which are formed by one same etch process including etching a drift oxide layer; a first gate and a second gate, which are formed by one same etch process including etching a poly silicon layer, a first P-type body region and a second P-type body region, which are formed by one same ion implantation process, a first N-type source and a first N-type drain, and a second N-type source and a second N-type drain.

Abstract: An integration manufacturing method of a depletion high voltage NMOS device and a depletion low voltage NMOS device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer; forming an N-type well in the depletion high voltage NMOS device region; forming a high voltage P-type well in the semiconductor layer, wherein the N-type well and the high voltage P-type well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer after the N-type well and the high voltage P-type well formed; forming a low voltage P-type well; and forming an N-type high voltage channel region and an N-type low voltage channel region, such that each of the depletion high voltage NMOS device and the depletion low voltage NMOS device is turned ON when a gate-source voltage thereof is zero voltage.

Abstract: An integration manufacturing method of a high voltage device and a low voltage device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer, for defining a high voltage device region and a low voltage device region; forming a first high voltage well in the high voltage device region; forming a second high voltage well in the semiconductor layer, wherein the first high voltage well and the second high voltage well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer, wherein the oxide layer overlays the high voltage device region and the low voltage device region; and forming a first low voltage well in the low voltage device region in the semiconductor layer.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.