Patents by Inventor Wu-Tung Cheng

Wu-Tung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11320487
    Abstract: A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; a test response compactor configured to compact the test responses; and shuffler circuitry inserted between outputs of the scan chains and inputs of the test response compactor, the shuffler circuitry comprising state elements configured to delay output signals from some of the scan chains for one or more clock cycles based on a control signal, the control signal varying with the test patterns.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: May 3, 2022
    Assignee: SIEMENS INDUSTRY SOFTWARE INC.
    Inventors: Wu-Tung Cheng, Chen Wang, Mark A. Kassab
  • Publication number: 20220065929
    Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Inventors: Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
  • Publication number: 20220043062
    Abstract: A circuit comprises a plurality of scan chains. The plurality of scan chains comprises bidirectional scan cells. Each of the bidirectional scan cells comprises two serial input-output ports serving as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in either a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.
    Type: Application
    Filed: February 11, 2020
    Publication date: February 10, 2022
    Inventors: Wu-Tung Cheng, Yu Huang
  • Patent number: 11156661
    Abstract: A circuit comprises a scan chain comprising one or more multi-bit flip-flops, a plurality of multiplexers, and new scan enable signal generation circuitry. Each of the plurality of multiplexers is associated with a particular bit of the one or more multi-bit flip-flops with an output of the each of the plurality of multiplexers coupled to a data input of the particular bit, which is configured to select, based on a scan direction control signal, between an input signal from functional circuitry of the circuit and an input signal from a data output of a bit of the scan chain immediately following the particular bit in a normal scan shift direction. The new scan enable signal generation circuitry is configured to generate a new scan enable signal for the one or more multi-bit flip-flops based on the scan direction control signal and a scan enable signal for the scan chain.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 26, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
  • Patent number: 11106848
    Abstract: This application discloses a computing system implementing an automatic test pattern generation tool can generate test patterns to apply to a reversible scan chain in an integrated circuit. The reversible scan chain can be configured to serially load and unload the test patterns in multiple directions to generate test responses. The computing system can implement a defect diagnosis tool to detect a presence of a suspected defect associated with the reversible scan chain based on the test responses, identify which of the multiple directions used to load and unload the test patterns corresponds to the suspected defect in the reversible scan chain based on the test responses, and determine a portion of the integrated circuit to inspect for a manufacturing fault corresponding to the suspected defect based, at least in part, on the identification of which of the multiple directions corresponds to the suspected defect in the reversible scan chain.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: August 31, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
  • Patent number: 11092645
    Abstract: A test pattern is shifted into scan chains in a circuit in a first direction. The scan cells on each of the scan chains are further coupled to corresponding scan cells on two other scan chains in the scan chains such that data bits stored in the scan cells can be shifted circularly in a second direction orthogonal to the first direction based on a control signal. The loaded test pattern is then shifted in the second direction for a number of clock cycles equal to the number of the scan chains. The test pattern is then shifted in the first direction out of the scan chains to generate a chain test result. Faulty scan cell candidates on faulty scan chains may be determined based on part of the chain test result for one of good scan chains.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 17, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Wu-Tung Cheng, Yu Huang
  • Patent number: 11073556
    Abstract: A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal. The first signal determines whether the plurality of scan chains operate in a first mode or a second mode. The plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test; the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: July 27, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Wu-Tung Cheng, Yu Huang
  • Patent number: 11041906
    Abstract: A system and method for performing scan chain testing is disclosed. Scan cells, in the form of scan chains, are inserted into circuit designs for testing those circuit designs. The integrity of the scan chains is checked for defects before testing the circuit under test. In order to do so, various scan chain patterns, including one or both of U-turn and Z-turn patterns, are used in order to generate scan chain test data. The scan chain test data is analyzed in order to identify one or both of a type of defect (e.g., a timing fault, stuck-at fault, etc.) or a location of the defect. Further, the scan chain testing is performed using chain patterns with adaptive length.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 22, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma
  • Publication number: 20210150111
    Abstract: This application discloses a computing system implementing an automatic test pattern generation tool can generate test patterns to apply to a reversible scan chain in an integrated circuit. The reversible scan chain can be configured to serially load and unload the test patterns in multiple directions to generate test responses. The computing system can implement a defect diagnosis tool to detect a presence of a suspected defect associated with the reversible scan chain based on the test responses, identify which of the multiple directions used to load and unload the test patterns corresponds to the suspected defect in the reversible scan chain based on the test responses, and determine a portion of the integrated circuit to inspect for a manufacturing fault corresponding to the suspected defect based, at least in part, on the identification of which of the multiple directions corresponds to the suspected defect in the reversible scan chain.
    Type: Application
    Filed: August 26, 2020
    Publication date: May 20, 2021
    Inventors: Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
  • Patent number: 11010523
    Abstract: One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers. The one, two, or three test pattern generation and encoding processes are configured to minimize active input channels for each of the compressed test patterns. A test pattern count for each of a plurality of input channel numbers is determined based on the compressed test patterns for the one or two input channel numbers, a number of active input channels for each of the compressed test patterns, and an assumption of similar input data volumes for different numbers of input channels. The test pattern count information can be employed to determine an optimal number of input channels for a test decompressor.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 18, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Yu Huang, Janusz Rajski, Mark A. Kassab, Wu-Tung Cheng
  • Patent number: 10977400
    Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
  • Publication number: 20210033669
    Abstract: A circuit comprises a scan chain comprising one or more multi-bit flip-flops, a plurality of multiplexers, and new scan enable signal generation circuitry. Each of the plurality of multiplexers is associated with a particular bit of the one or more multi-bit flip-flops with an output of the each of the plurality of multiplexers coupled to a data input of the particular bit, which is configured to select, based on a scan direction control signal, between an input signal from functional circuitry of the circuit and an input signal from a data output of a bit of the scan chain immediately following the particular bit in a normal scan shift direction. The new scan enable signal generation circuitry is configured to generate a new scan enable signal for the one or more multi-bit flip-flops based on the scan direction control signal and a scan enable signal for the scan chain.
    Type: Application
    Filed: July 20, 2020
    Publication date: February 4, 2021
    Inventors: Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
  • Publication number: 20200410065
    Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 31, 2020
    Inventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
  • Publication number: 20200341057
    Abstract: A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal. The first signal determines whether the plurality of scan chains operate in a first mode or a second mode. The plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test; the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 29, 2020
    Inventors: Wu-Tung Cheng, Yu Huang
  • Publication number: 20200333398
    Abstract: A system and method for performing scan chain testing is disclosed. Scan cells, in the form of scan chains, may be inserted into circuit designs for testing those circuit designs. Because the scan chains themselves may be defective, the integrity of scan chains may be checked first before testing the circuit under test. In order to do so, various scan chain patterns, including one or both of U-turn and Z-turn patterns, may be used in order to generate scan chain test data. The scan chain test data may then be analyzed in order to identify one or both of a type of defect (e.g., a timing fault, stuck-at fault, etc.) or a location of the defect. Further, the scan chain testing may be performed using chain patterns with adaptive length.
    Type: Application
    Filed: August 23, 2019
    Publication date: October 22, 2020
    Inventors: Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma
  • Patent number: 10795751
    Abstract: Various aspects of the disclosed technology relate to techniques of logic diagnosis based on cell-aware diagnostic pattern generation. A first diagnosis process is performed on a failed integrated circuit based on a first fail log to generate a first set of defect suspects. The first fail log is generated by applying the first set of test patterns to the failed integrated circuit in a first scan-based test. A second set of test patterns are generated using fault models for internal defects in one or more cells included in the first set of defect suspects. The second set of test patterns are applied to the failure integrated circuit to generate a second fail log. A second diagnosis process is performed on the failure integrated circuit based on the second fail log.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 6, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Huaxing Tang, Manish Sharma, Wu-Tung Cheng
  • Publication number: 20200302321
    Abstract: A computing system may include a model training engine configured to train a supervised learning model with a training set comprising training probability distributions computed for training dies through a local phase of a volume diagnosis procedure. The computing system may also include a volume diagnosis adjustment engine configured to access a diagnosis report for a given circuit die that has failed scan testing and compute, through the local phase of the volume diagnosis procedure, a probability distribution for the given circuit die from the diagnosis report. The volume diagnosis adjustment engine may also adjust the probability distribution into an adjusted probability distribution using the supervised learning model and provide the adjusted probability distribution for the given circuit die as an input to a global phase of the volume diagnosis procedure to determine a global root cause distribution for multiple circuit dies that have failed the scan testing.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Yue Tian
  • Publication number: 20200166571
    Abstract: A test pattern is shifted into scan chains in a circuit in a first direction. The scan cells on each of the scan chains are further coupled to corresponding scan cells on two other scan chains in the scan chains such that data bits stored in the scan cells can be shifted circularly in a second direction orthogonal to the first direction based on a control signal. The loaded test pattern is then shifted in the second direction for a number of clock cycles equal to the number of the scan chains. The test pattern is then shifted in the first direction out of the scan chains to generate a chain test result.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 28, 2020
    Inventors: Wu-Tung Cheng, Yu Huang
  • Patent number: 10592625
    Abstract: Logic diagnosis is performed on failing reports of defective integrated circuits to derive a diagnosis report for each of the failing reports which comprise information of suspects. The suspects comprise cell internal suspects and interconnect suspects. A probability distribution of root causes for causing the defective integrated circuits is determined to maximize a likelihood of observing the diagnosis reports based on a probability for each of the suspects given each of the root causes and a probability for each of the diagnosis reports given each of the suspects. The probability for each of the diagnosis reports given each of the cell internal suspects is weighted higher than the probability for each of the diagnosis reports given each of the interconnect suspects.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: March 17, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Gaurav Veda
  • Patent number: 10496779
    Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: December 3, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Robert Brady Benware, Wu-Tung Cheng, Christopher Schuermyer, Jonathan J. Muirhead, Chen-Yi Chang