Abstract: Various aspects of the disclosed technology relate to cell internal defect diagnosis techniques. Defect candidates are first determined based on path-tracing through a circuit design. Then, cell internal defect suspects are determined from the defect candidates based on simulating failing test patterns by using cell internal fault models. The defect candidate determination may be further based on simulating the failing test patterns by using conventional fault models. The cell internal defect suspect determination may be further based on simulating passing test patterns by using the cell internal fault models.

Abstract: A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified.

Abstract: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.

Abstract: A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models.

Abstract: Aspects of the invention relate to techniques for cycle-based scan chain diagnosis for integrated circuits with embedded compactors. With various implementations of the invention, no-failing-bits output channels of a compactor are first identified based on output data of a test. Next, good scan chains are identified based on scan chains associated with the no-failing-bits output channels. From scan chains other than the good scan chains, analysis of bits outputted from failing-bits output channels per clock cycle is performed to identify suspected faulty scan chains.

Abstract: Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.

Abstract: Aspects of the disclosed technology relate to techniques for determining canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises: performing a translation on the coordinates of vertices based on differences between maximum and minimum X/Y coordinate values of the vertices. Based on sums of X/Y coordinate values of the new coordinates of the vertices, a canonical form of the geometric elements is determined. The canonical form coordinates of the vertices may then be determined and sorted. The sorted canonical form coordinates may be employed for pattern matching.

Abstract: Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.

Abstract: Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design are analyzed to determine information of potential logic relationship between the scan cells. The information of potential logic relationship between the scan cells may comprise information of fan-in cones for the scan cells. Based at least in part on the information of potential logic relationship between the scan cells, scan chains may be formed. The formation of scan chains may be further based on layout information of the circuit design. The formation of scan chains may be further based on compactor information of the circuit design.

Abstract: Aspects of the disclosed techniques relate to techniques for identifying power sensitive scan cells. Signal probability values for signal lines in a circuit design are first computed, wherein the signal lines comprise signal lines associated with scan cells in the circuit design. Toggling probability values are then computed based on the signal probability values, wherein the toggling probability values comprise toggling rate values for the scan cells. Toggling rate reduction values are then computed based on the toggling probability values, wherein the toggling rate reduction values comprise toggling rate reduction values for the scan cells. Finally, scan cells having high toggling rate reduction values are identified.

Abstract: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.

Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.

Abstract: Aspects of the invention relate to techniques for diagnosing compound hold-time faults. A profiling-based scan chain diagnosis may be performed on a faulty scan chain to determine observed scan cell failing probability information and one or more faulty segments based on scan pattern test information. Calculated scan cell failing probability information may then be derived. Based on the calculated scan cell failing probability information and the observed scan cell failing probability information, one or more validated faulty segments are verified to have one or more compound hold-time faults. Finally, one or more clock defect suspects may be identified based on information of the one or more validated faulty segments.

Abstract: With various implementations of the invention, unloading masking information for each of the scan patterns is first determined. A tester then applies the scan patterns to a circuit under test and collects test response data according to the unloading masking information. A profiling-based analysis is performed to determine failing scan cell information based on the test response data.

Abstract: Aspects of the invention relate to techniques of testing interconnects in stacked designs for leakage defects. Logic “1” or “0” is first applied to one end of an interconnect during a first pulse. Then, logic value at the one end is captured, which triggered by an edge of a second pulse. The first pulse precedes the second pulse by a time period being selected from a plurality of delay periods. The plurality of delay periods is generated by a device shared by a plurality of interconnects.

Abstract: Aspects of the invention relate to ring-oscillator-based test architecture for characterizing interconnects in stacked designs. The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by control circuitry.

Abstract: Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

Abstract: Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers.

Abstract: A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified.