Abstract: The present invention provides a readout integrated circuit and an operation method thereof. The readout integrated circuit includes a readout circuit, a line buffer and a communication interface circuit. The readout circuit reads out a plurality of row sensing results of a plurality of sensor rows of a sensor. The line buffer is coupled to the readout circuit for temporarily storing a current row sensing result of a current sensor row of the sensor. The communication interface circuit is coupled to the line buffer. After the current row sensing result of the current sensor row is temporarily stored into the line buffer, the communication interface circuit outputs the current row sensing result in real time to a host circuit.

Abstract: According to an aspect, a computer-implemented method includes accessing a profile of a user that indicates a likelihood that the user will execute each of a plurality of types of processing when training a new AI model. A runtime matrix that includes identifiers of runtime environments is accessed. The matrix also includes, for each of the runtime environments, a frequency of use of the runtime environment to train previously trained AI models using each of the plurality of types of processing. One or more of the runtime environments is selected for output to the user based at least in part on the profile of the user and the runtime matrix. Identifiers of the selected one or more of the runtime environments are output to a user interface of the user along with a suggestion to use one of the selected one or more of the runtime environments.

Abstract: A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: The present disclosure provides an audio compression device, an audio compressing system and an audio compression method. The audio compression device comprises a first transceiver and a first processor. The first transceiver is connected to the first processor. The processor obtains an audio signal and an available bandwidth, and the processor performs an audio compression encoding on the audio signal to obtain a sample audio signal, and then compares with the audio signal and the sample audio signal to generate a residual signal, and the residual signal is transmitted according to the available bandwidth. The audio signal can be completely transmitted to an audio decompression device to reduce the distortion of the audio signal.

Abstract: A semiconductor device includes: a substrate, including an upper surface and a first to a fourth side surfaces; wherein the upper surface includes a first edge connecting the first side surface and a second edge opposite to the first edge and connecting the second side surface; a first modified trace formed on the first side surface; and a semiconductor stack formed on the upper surface, including a lower surface connecting the upper surface of the substrate, and the lower surface comprises a fifth edge adjacent to the first edge and a sixth edge opposite to the fifth edge and adjacent to the second edge; wherein a shortest distance between the first edge and the fifth edge is S1 ?m, and a shortest distance between the second edge and the sixth edge is S2 ?m; wherein in a lateral view viewing from the third side surface, the first side surface forms a first acute angle with a degree of ?1 with the vertical direction, the second side surface forms a second acute angle with a degree of ?2 with the vertical dire

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.

Abstract: A semiconductor structure includes an active layer, a first gate insulator layer disposed over the active layer, a first gate layer disposed over the gate insulator layer, at least one charged layer disposed between the first gate insulator layer and the active layer, and a pair of contact structures disposed over the active layer. The at least one charged layer includes an oxide material.

Abstract: The present invention provides a readout integrated circuit and an operation method thereof. The readout integrated circuit includes a readout circuit, a line buffer and a communication interface circuit. The readout circuit reads out a plurality of row sensing results of a plurality of sensor rows of a sensor. The line buffer is coupled to the readout circuit for temporarily storing a current row sensing result of a current sensor row of the sensor. The communication interface circuit is coupled to the line buffer. After the current row sensing result of the current sensor row is temporarily stored into the line buffer, the communication interface circuit outputs the current row sensing result in real time to a host circuit.

Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.

Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Abstract: An augmented reality implementing method applied to a server, which includes a plurality of augmented reality objects and a plurality of setting records corresponding to the augmented reality objects respectively is provided. Firstly, the server receives an augmented reality request from a mobile device, where the augmented reality request is related to a target device. Then, the server is communicated with the target device to access current information. Then, the server determines the current information corresponds to which one of the setting records, and selects one of the augmented reality objects based on the determined setting record as a virtual object provided to the mobile device.

Abstract: A chip capable of controlling a panel to perform fingerprint sensing is provided. Fingerprint sensing pixels of the panel are divided into a plurality of fingerprint zones along a first direction. The chip includes a control circuit. The control circuit provides multiple control signals for controlling the panel to perform fingerprint sensing. The control signals include multiple start pulse signals. The start pulse signals are used to indicate the selected fingerprint zone. The number of the fingerprint zones is greater than the number of the start pulse signals.

Abstract: An e-gifting method is provided. The method is performed by a computer device including a processing unit, and includes: receiving, by the processing unit, gift filtering information and receiver information from a giver terminal device; generating, by the processing unit, a candidate gift list according to the gift filtering information and the receiver information, where the candidate gift list includes a plurality of candidate gift items; generating, by the processing unit, a gifting list from the candidate gift items according to giver selecting information from the giver terminal device, where the gifting list includes a plurality of gifting gift items; confirming, by the processing unit, a selected gift item from the gifting gift items according to receiver selecting information from a receiver terminal device; and transmitting, by the processing unit, payment information corresponding to the selected gift item to the giver terminal device.

Abstract: A semiconductor device and a lead frame. The semiconductor device comprises at least one semiconductor chip that is attached to a surface of a base island in a first plane, wherein a connecting rib is connected to the base island, and has a first part which is obliquely connected to the base island; the connecting rib has a second part, and the second part has a surface in a second plane; the second plane is parallel to the first plane and is a plane different from the first plane; the connecting rib has a branch part divided from the second part and the branch part has, in the second plane, a surface used for receiving a lead connected to the semiconductor chip; and the branch part has an edge which is distant from a first edge of the base island by a first distance.

Abstract: Disclosed are a packaging substrate, a grid array package, and a preparation method therefor. The packaging substrate comprises a plurality of packaging units, and each packaging unit is defined by a closed packaging line. The packaging substrate comprises: a base substrate having a first surface and a second surface that are opposite to each other, a plurality of solder pads provided on the first surface, and a metal layer provided on the second surface. In a given packaging unit, the metal layer comprises a plurality of lead pads, at least one lead pad extending from an inner side of the packaging unit defined by the packaging line to an outer side. The lead pad is connected to one solder pad by means of a connecting member penetrating through the base substrate, and an orthographic projection of the connecting member on the base substrate at least partially covers the packaging line.