Patents by Inventor Wu Wei

Wu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222519
    Abstract: A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.
    Type: Application
    Filed: March 11, 2024
    Publication date: July 4, 2024
    Inventors: Wu-Wei Tsai, Hai-Ching Chen
  • Publication number: 20240212551
    Abstract: An integrated driving device is provided. The integrated driving device includes a touch sensing circuit and an optical sensing circuit. The touch sensing circuit is configured to perform touch sensing in a plurality of touch sensing periods during a first frame period. The optical sensing circuit is configured to perform optical sensing during at least one optical sensing period during the first frame period to obtain optical sensing signals for generating first ambient light information. The touch sensing periods and the optical sensing period are non-overlapping. Correspondingly, an operation method of an integrated driving device is also provided.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Wei-Lun Shih, Wu-Wei Lin, Jiun-Jie Tsai, Huang-Chin Tang, Ching-Chun Lin
  • Patent number: 12014564
    Abstract: An electronic circuit adapted to control an operation of a gate driver circuit is provided. The electronic circuit includes a gate control circuit. The gate control circuit outputs control signals to the gate driver circuit in a display period and a fingerprint sensing period via the same output nodes. The control signals include a start pulse signal and a switch control signal. The switch control signal controls the gate driver circuit to operate in the display period or the fingerprint sensing period. The gate driver circuit includes a plurality of shift register groups and a switch circuit. The shift register groups output scan signals according to the start pulse signal. The switch circuit receives and outputs the scan signals to display scan lines in the display period and outputs the scan signals to fingerprint scan lines in the fingerprint sensing period according to the switch control signal.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: June 18, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Wei-Lun Shih, Wu Wei Lin, Kuei Jung Chen
  • Patent number: 11984508
    Abstract: A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wu-Wei Tsai, Po-Ting Lin, Hai-Ching Chen, Chung-Te Lin
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11967168
    Abstract: A method and device of fingerprint image generation for saving memory. The method includes generating a first fingerprint image of an original data size according to a plurality of first analog sensing signals which are read from a fingerprint sensor array before an exposure period ends. Then the first fingerprint image represented by a first data size which is equivalent to or smaller than the original data size is stored. a second fingerprint image of the original data size is generated after generating the first fingerprint image of the original data size according to a plurality of second analog sensing signals which are read from the fingerprint sensor array during the exposure period. The second fingerprint image represented by a compressed data size smaller than the original data size is then stored.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: April 23, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Weilun Shih, Wu-Wei Lin
  • Patent number: 11961584
    Abstract: The present invention provides a readout integrated circuit and an operation method thereof. The readout integrated circuit includes a readout circuit, a line buffer and a communication interface circuit. The readout circuit reads out a plurality of row sensing results of a plurality of sensor rows of a sensor. The line buffer is coupled to the readout circuit for temporarily storing a current row sensing result of a current sensor row of the sensor. The communication interface circuit is coupled to the line buffer. After the current row sensing result of the current sensor row is temporarily stored into the line buffer, the communication interface circuit outputs the current row sensing result in real time to a host circuit.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: April 16, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventor: Wu Wei Lin
  • Patent number: 11955561
    Abstract: A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wu-Wei Tsai, Hai-Ching Chen
  • Publication number: 20240113225
    Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Wei Tsai, Yan-Yi Chen, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240113222
    Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.
    Type: Application
    Filed: January 3, 2023
    Publication date: April 4, 2024
    Inventors: Yan-Yi Chen, Wu-Wei Tsai, Yu-Ming Hsiang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11948884
    Abstract: A semiconductor device includes: a substrate, including an upper surface and a first to a fourth side surfaces; wherein the upper surface includes a first edge connecting the first side surface and a second edge opposite to the first edge and connecting the second side surface; a first modified trace formed on the first side surface; and a semiconductor stack formed on the upper surface, including a lower surface connecting the upper surface of the substrate, and the lower surface comprises a fifth edge adjacent to the first edge and a sixth edge opposite to the fifth edge and adjacent to the second edge; wherein a shortest distance between the first edge and the fifth edge is S1 ?m, and a shortest distance between the second edge and the sixth edge is S2 ?m; wherein in a lateral view viewing from the third side surface, the first side surface forms a first acute angle with a degree of ?1 with the vertical direction, the second side surface forms a second acute angle with a degree of ?2 with the vertical dire
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 2, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Lin Tzu Hsiang, Chen Chih Hao, Wu Wei Che, Chen Ying Chieh
  • Patent number: 11922844
    Abstract: An integrated driving device is provided. The integrated driving device includes a touch sensing circuit and an optical sensing circuit. The touch sensing circuit is configured to perform touch sensing in a plurality of touch sensing periods during a first frame period. The optical sensing circuit is configured to perform optical sensing during at least one optical sensing period during the first frame period to obtain optical sensing signals for generating first ambient light information. The touch sensing periods and the optical sensing period are non-overlapping. Correspondingly, an operation method of an integrated driving device is also provided.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Wei-Lun Shih, Wu-Wei Lin, Jiun-Jie Tsai, Huang-Chin Tang, Ching-Chun Lin
  • Publication number: 20240038854
    Abstract: A semiconductor structure includes an active layer, a first gate insulator layer disposed over the active layer, a first gate layer disposed over the gate insulator layer, at least one charged layer disposed between the first gate insulator layer and the active layer, and a pair of contact structures disposed over the active layer. The at least one charged layer includes an oxide material.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Wei Tsai, Yan-Yi Chen, Yu-Ming Hsiang, Hai-Ching Chen, Chung-Te Lin
  • Publication number: 20240013817
    Abstract: The present invention provides a readout integrated circuit and an operation method thereof. The readout integrated circuit includes a readout circuit, a line buffer and a communication interface circuit. The readout circuit reads out a plurality of row sensing results of a plurality of sensor rows of a sensor. The line buffer is coupled to the readout circuit for temporarily storing a current row sensing result of a current sensor row of the sensor. The communication interface circuit is coupled to the line buffer. After the current row sensing result of the current sensor row is temporarily stored into the line buffer, the communication interface circuit outputs the current row sensing result in real time to a host circuit.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 11, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventor: Wu Wei Lin
  • Publication number: 20240008287
    Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.
    Type: Application
    Filed: July 4, 2022
    Publication date: January 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Ting Lin, Wei-Chih Wen, Kai-Wen Cheng, Wu-Wei Tsai, Yu-Ming Hsiang, Yan-Yi Chen, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240006538
    Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.
    Type: Application
    Filed: July 3, 2022
    Publication date: January 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Wei Tsai, Po-Ting Lin, Kai-Wen Cheng, Sai-Hooi Yeong, Han-Ting Tsai, Ya-Ling Lee, Hai-Ching Chen, Chung-Te Lin, Yu-Ming Lin
  • Publication number: 20230378369
    Abstract: A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 23, 2023
    Inventors: Wu-Wei TSAI, Po-Ting LIN, Hai-Ching CHEN, Chung-Te LIN
  • Publication number: 20230369439
    Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Wu-Wei TSAI, Chun-Chieh LU, Hai-Ching CHEN, Yu-Ming LIN, Sai-Hooi YEONG
  • Publication number: 20230326146
    Abstract: An augmented reality implementing method applied to a server, which includes a plurality of augmented reality objects and a plurality of setting records corresponding to the augmented reality objects respectively is provided. Firstly, the server receives an augmented reality request from a mobile device, where the augmented reality request is related to a target device. Then, the server is communicated with the target device to access current information. Then, the server determines the current information corresponds to which one of the setting records, and selects one of the augmented reality objects based on the determined setting record as a virtual object provided to the mobile device.
    Type: Application
    Filed: October 4, 2022
    Publication date: October 12, 2023
    Inventors: Kuo-Chung CHIU, Hsuan-Wu WEI, Yen-Ting LIU, Shang-Chih LIANG, Shih-Hua MA, Yi-Hsuan TSAI, Jun-Ting CHEN, Kuan-Ling CHEN
  • Patent number: 11749012
    Abstract: A chip capable of controlling a panel to perform fingerprint sensing is provided. Fingerprint sensing pixels of the panel are divided into a plurality of fingerprint zones along a first direction. The chip includes a control circuit. The control circuit provides multiple control signals for controlling the panel to perform fingerprint sensing. The control signals include multiple start pulse signals. The start pulse signals are used to indicate the selected fingerprint zone. The number of the fingerprint zones is greater than the number of the start pulse signals.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: September 5, 2023
    Assignee: Novatek Microelectronics Corp.
    Inventors: Wei-Lun Shih, Wu-Wei Lin, Huang-Chin Tang, Ting-Hsuan Hung