Abstract: Methods and apparatus to provide a clustered variations-aware architecture are described. In one embodiment, one or more variations within a clock domain are detected and utilized to adjust a clock signal of the clock domain.

Abstract: Embodiments of apparatuses and methods for reducing the soft error vulnerability of stored data are disclosed. In one embodiment, an apparatus includes storage logic, determination logic, and selection logic. The determination logic is to determine a condition of a dataword. The storage logic includes logic to store a first portion of the dataword, a second portion of the dataword, and a result generated by the determination logic. The selection logic is to select, based on the contents of the storage logic to store the result, either the contents of the storage logic to store the second portion of the dataword, or a replacement value. The replacement value depends on the contents of a predetermined bit of the storage logic to store the first portion of the dataword.

Abstract: A processor including a pipeline for processing a plurality of instructions is disclosed. The pipeline comprises a plurality of stages. Each stage comprises a processing logic, and a control logic. The processing logic processes an input to produce an output. The control logic receives the output of the processing logic, and provides an intermediate and final output of the processing logic. The intermediate output is provided at a fraction of one cycle of a clock signal after receiving the input. The final output is produced at one cycle of a clock signal after receiving the input. The control logic also detects errors, and stalls the pipeline for one cycle of the clock signal when an error is detected.