Abstract: Method and apparatus for virus scanning, and a non-transitory computer-readable medium that stores instructions for performing virus scanning. The method includes detecting a status of a system; and when the status of the system is idle, if current virus scanning has begun, continuing the current virus scanning, and if the current virus scanning has not begun, acquiring a scanning progress of previous virus scanning, beginning the current virus scanning according to the acquired scanning progress, and recording a scanning progress of the current virus scanning.

Abstract: Method and apparatus for virus scanning, and a non-transitory computer-readable medium that stores instructions for performing virus scanning. The method includes detecting a status of a system; and when the status of the system is idle, if current virus scanning has begun, continuing the current virus scanning, and if the current virus scanning has not begun, acquiring a scanning progress of previous virus scanning, beginning the current virus scanning according to the acquired scanning progress, and recording a scanning progress of the current virus scanning.

Abstract: A radiation hardened master latch for use in a programmable phase frequency divider operating at GHz frequencies is implemented in deep submicron CMOS technology, and consists of two identical half circuits interconnected in a DICE-type configuration that makes the master latch immune to a single event upset (SEU) affecting at most one of its four data inputs. Each half circuit includes a clock input circuit with four sub-clock nodes each coupled by an inverter to a common clock input. The clock input circuit is configured to be redundant, such that the operation of the master latch half circuit is also immune to an SEU affecting at most one the inverters associated with the plurality of sub-clock nodes. The radiation hardened master latch resides in a design structure embodied in a machine readable medium storing information for designing, manufacturing and/or testing the master latch.

Abstract: A radiation hardened master latch for use in a programmable phase frequency divider operating at GHz frequencies is implemented in deep submicron CMOS technology, and consists of two identical half circuits interconnected in a DICE-type configuration that makes the master latch immune to a single event upset (SEU) affecting at most one of its four data inputs. Each half circuit includes a clock input circuit with four sub-clock nodes each coupled by an inverter to a common clock input. The clock input circuit is configured to be redundant, such that the operation of the master latch half circuit is also immune to an SEU affecting at most one the inverters associated with the plurality of sub-clock nodes. The radiation hardened master latch resides in a design structure embodied in a machine readable medium storing information for designing, manufacturing and/or testing the master latch.