Abstract: A method of forming a semiconductor structure includes: providing an initial substrate having a first region and a second region; forming a first substrate on the initial substrate; forming a first insulating layer on the first substrate; forming a second substrate on the first insulating layer; removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.

Abstract: Systems and methods provide reception of a call to a first function, determination of a first configuration file associated with the first function, the first configuration file indicating a primary function, a secondary function and a relationship between a first property of the primary function and a second property of the secondary function, calling of the primary function and reception of a corresponding first result set, calling of the secondary function, the call to the secondary function including a filter on the second property based on values of the first result set associated with the first property, reception of a second result set corresponding to the call to the secondary function, generation of a composed result set based on the first result set, the second result set, and the relationship, and return of the composed result set in response to the call to the first function.

Abstract: An optical device and its fabrication method are provided. The method includes: providing a substrate including a coupling region; forming a first dielectric layer on the substrate; forming an initial waveguide groove in the first dielectric layer on the coupling region; forming a patterned layer on a surface of the first dielectric layer and in the initial waveguide groove, exposing at least a portion of a bottom of the initial waveguide groove; and using the patterned layer as a mask to etch the first dielectric layer, to form a waveguide structure on the substrate. The waveguide structure includes a waveguide end structure on the coupling region.

Abstract: A method of forming a semiconductor structure includes: providing an initial substrate having a first region and a second region; forming a first substrate on the initial substrate; forming a first insulating layer on the first substrate; forming a second substrate on the first insulating layer; removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.

Abstract: The invention provides a printed circuit board and a detection method for detecting a connection between the printed circuit board and a flexible circuit board, and a display panel. The printed circuit board, through a connector provided thereon, is connected to a flexible circuit board, the printed circuit board is provided thereon with at least one first detection structure for matching with at least one second detection structure provided on the flexible circuit board, and whether or not a connection between the printed circuit board and the flexible circuit board is correct is determined by detecting matching between the first detection structures and the second detection structures. Pins of the printed circuit board may be correctly connected to pins of the flexible circuit board, and a case that short circuit occurs and thus the signal lines are damaged and burned can be avoided.

Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.

Abstract: A display panel and a driving method therefor and a display apparatus are provided. The display panel includes a plurality of gate lines and a plurality of data lines, which intersect with each other, each of the data lines has an input terminal, and input terminals of the data lines are provided at a first side of the display panel, the driving method comprises: sequentially applying a gate signal to each of the gate lines, and applying data signals to the data lines through the input terminals while any of the gate lines is applied with a gate signal, wherein the gate signal satisfies conditions that Ta(i)?Ta(i+1) and Ta(1)<Ta(n), where Ta(i) is a duration of the gate signal applied to the ith gate line starting from the first side, 1?i?n?1, where n is a total number of the gate lines.

Abstract: The present disclosure directs to a light-emitting device configured for attachment onto a container. The device comprises a bottom layer and a filling layer atop with a central cavity to house electronic components arranged onto a circuit board, wherein the filling layer further comprises at least one extension, one cutout notch, and at least one light emitting LED arranged onto the circuit board around the extension. A bonding layer covers the top surface of the filling layer with a removable isolation paper. The circuit board and electronic components are protected form liquid corrosion and from blunt force while adhered onto the container.

Abstract: A display panel and a driving method therefor and a display apparatus are provided. The display panel includes a plurality of gate lines and a plurality of data lines, which intersect with each other, each of the data lines has an input terminal, and input terminals of the data lines are provided at a first side of the display panel, the driving method comprises: sequentially applying a gate signal to each of the gate lines, and applying data signals to the data lines through the input terminals while any of the gate lines is applied with a gate signal, wherein the gate signal satisfies conditions that Ta(i)?Ta(i+1) and Ta(1)<Ta(n), where Ta(i) is a duration of the gate signal applied to the ith gate line starting from the first side, 1?i?n?1, where n is a total number of the gate lines.

Abstract: A driver IC for driving a display panel, a display device and a method for driving the driver IC are provided. The driver IC is provided with N pins corresponding to N signal transmission lines of the display panel respectively. Each pin is connected to one corresponding signal transmission line through one transmission wire. The N pins include a first pin and a second pin. The transmission wires include a first transmission wire connected to the first pin and a second transmission wire connected to the second pin and having a length less than the first transmission wire. The driver IC includes a signal generation module configured to generate N driving signals. The N driving signals include a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin and having a current intensity less than the first driving signal.

Abstract: The present invention relates to a process for producing a polyurethane sealant, which comprises mixing (a) polyisocyanate, (b) polyetherpolyols, (c) aliphatic, exclusively amine initiated alkoxylation products having an OH-number of 400 to 1000 mg KOH/g and a functionality of 4, (d) blowing agents and optionally (e) chain extenders and/or crosslinking agents, (f) catalysts and (g) auxiliaries and/or additives to give a reaction mixture and reacting the reaction mixture to give the polyurethane sealant. The present invention further relates to a cast in place polyurethane sealant, obtained according to a process according to the present invention.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.

Abstract: The present disclosure directs to a light emitting device for a container, including: a pad and a circuit board arranged on the pad, wherein an electronic element is arranged on an upper layer and/or a lower layer of the circuit board, a filling layer is further arranged on the pad, a bonding material layer is arranged on the surface of the filling layer, a removable isolation layer is adhered on the bonding material layer, and the bonding material layer is attached to the container; and a middle area of the filling layer is provided with a hollow area to expose the electronic element on the circuit board, and at least one inward extension part in the hollow area of the filling layer is placed above the circuit board. In usage, the circuit board is protected as much as possible, liquid is prevented from splashing onto the circuit board, meanwhile the risk that the liquid permeates into the circuit board is reduced, and the use reliability of the light emitting device is improved.

Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metallization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.

Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.

Abstract: A driver IC for driving a display panel, a display device and a method for driving the driver IC are provided. The driver IC is provided with N pins corresponding to N signal transmission lines of the display panel respectively. Each pin is connected to one corresponding signal transmission line through one transmission wire. The N pins include a first pin and a second pin. The transmission wires include a first transmission wire connected to the first pin and a second transmission wire connected to the second pin and having a length less than the first transmission wire. The driver IC includes a signal generation module configured to generate N driving signals. The N driving signals include a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin and having a current intensity less than the first driving signal.

Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: There are provided a GOA circuit, an array substrate, a display device and a driving method. The GOA circuit includes clock signal input lines and more than two GOA units connected in cascade, wherein each of the GOA units includes a selection signal output sub-unit and a selection sub-unit; the selection signal output sub-unit is configured to receive a source signal, and output a selection signal in accordance with the source signal; the selection sub-unit receives the selection signal and N clock signals, and outputs the received signal in accordance with the selection signal; and the clock signal input lines are no less than a number of N, and are configured to input the clock signals to the selection sub-unit, where N is an integer number which is higher than or equal to two. The gate driving structure of the GOA circuit, the array substrate and the display device occupies a small area. The driving method can achieve a single dot polarity inversion.