Patents by Inventor Xia Feng

Xia Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10359160
    Abstract: The present disclosure directs to a light-emitting device configured for attachment onto a container. The device comprises a bottom layer and a filling layer atop with a central cavity to house electronic components arranged onto a circuit board, wherein the filling layer further comprises at least one extension, one cutout notch, and at least one light emitting LED arranged onto the circuit board around the extension. A bonding layer covers the top surface of the filling layer with a removable isolation paper. The circuit board and electronic components are protected form liquid corrosion and from blunt force while adhered onto the container.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 23, 2019
    Inventor: Xia Feng
  • Publication number: 20190206353
    Abstract: A display panel and a driving method therefor and a display apparatus are provided. The display panel includes a plurality of gate lines and a plurality of data lines, which intersect with each other, each of the data lines has an input terminal, and input terminals of the data lines are provided at a first side of the display panel, the driving method comprises: sequentially applying a gate signal to each of the gate lines, and applying data signals to the data lines through the input terminals while any of the gate lines is applied with a gate signal, wherein the gate signal satisfies conditions that Ta(i)?Ta(i+1) and Ta(1)<Ta(n), where Ta(i) is a duration of the gate signal applied to the ith gate line starting from the first side, 1?i?n?1, where n is a total number of the gate lines.
    Type: Application
    Filed: July 20, 2018
    Publication date: July 4, 2019
    Inventors: Zhiwei ZHANG, Xia FENG
  • Publication number: 20190163864
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Publication number: 20190163865
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu
  • Patent number: 10304398
    Abstract: A driver IC for driving a display panel, a display device and a method for driving the driver IC are provided. The driver IC is provided with N pins corresponding to N signal transmission lines of the display panel respectively. Each pin is connected to one corresponding signal transmission line through one transmission wire. The N pins include a first pin and a second pin. The transmission wires include a first transmission wire connected to the first pin and a second transmission wire connected to the second pin and having a length less than the first transmission wire. The driver IC includes a signal generation module configured to generate N driving signals. The N driving signals include a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin and having a current intensity less than the first driving signal.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: May 28, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Liangliang Zheng, Jian He, Xia Feng, Tingting Jin
  • Patent number: 10289269
    Abstract: An electronic device for displaying an operation panel is provided in accordance with an aspect of the present disclosure. The operation panel displayed on a screen of the electronic device includes multiple levels of menus. The electronic device displays a first menu of the operation panel on the screen. When a second item being a subordinate item of a first item is selected, the electronic device hides the first menu showing the first item, and displays a second menu of the operation panel on the screen. The second menu includes a central section for identifying the second item.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 14, 2019
    Assignee: Hewett-Packard Development Company, L.P.
    Inventors: Di Yao, Qi-Feng Tang, Xia Meng, Zhen-Ping Zhang
  • Patent number: 10280248
    Abstract: The present invention relates to a process for producing a polyurethane sealant, which comprises mixing (a) polyisocyanate, (b) polyetherpolyols, (c) aliphatic, exclusively amine initiated alkoxylation products having an OH-number of 400 to 1000 mg KOH/g and a functionality of 4, (d) blowing agents and optionally (e) chain extenders and/or crosslinking agents, (f) catalysts and (g) auxiliaries and/or additives to give a reaction mixture and reacting the reaction mixture to give the polyurethane sealant. The present invention further relates to a cast in place polyurethane sealant, obtained according to a process according to the present invention.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: May 7, 2019
    Assignee: BASF SE
    Inventors: Yue Xia Feng, Cheun Gwo Chen, Andreas Emge, Jia Liang Di
  • Patent number: 10204866
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 12, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 10163815
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Xia Feng, Kang Chen, Jianmin Fang
  • Publication number: 20170363259
    Abstract: The present disclosure directs to a light emitting device for a container, including: a pad and a circuit board arranged on the pad, wherein an electronic element is arranged on an upper layer and/or a lower layer of the circuit board, a filling layer is further arranged on the pad, a bonding material layer is arranged on the surface of the filling layer, a removable isolation layer is adhered on the bonding material layer, and the bonding material layer is attached to the container; and a middle area of the filling layer is provided with a hollow area to expose the electronic element on the circuit board, and at least one inward extension part in the hollow area of the filling layer is placed above the circuit board. In usage, the circuit board is protected as much as possible, liquid is prevented from splashing onto the circuit board, meanwhile the risk that the liquid permeates into the circuit board is reduced, and the use reliability of the light emitting device is improved.
    Type: Application
    Filed: May 9, 2017
    Publication date: December 21, 2017
    Inventor: Xia Feng
  • Patent number: 9754867
    Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metallization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 5, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Publication number: 20170236788
    Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Xia Feng, Kang Chen
  • Publication number: 20170186388
    Abstract: A driver IC for driving a display panel, a display device and a method for driving the driver IC are provided. The driver IC is provided with N pins corresponding to N signal transmission lines of the display panel respectively. Each pin is connected to one corresponding signal transmission line through one transmission wire. The N pins include a first pin and a second pin. The transmission wires include a first transmission wire connected to the first pin and a second transmission wire connected to the second pin and having a length less than the first transmission wire. The driver IC includes a signal generation module configured to generate N driving signals. The N driving signals include a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin and having a current intensity less than the first driving signal.
    Type: Application
    Filed: October 9, 2015
    Publication date: June 29, 2017
    Applicants: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Liangliang ZHENG, Jian HE, Xia FENG, Tingting JIN
  • Patent number: 9679863
    Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 13, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Xia Feng, Kang Chen
  • Patent number: 9666500
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 30, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Patent number: 9626922
    Abstract: There are provided a GOA circuit, an array substrate, a display device and a driving method. The GOA circuit includes clock signal input lines and more than two GOA units connected in cascade, wherein each of the GOA units includes a selection signal output sub-unit and a selection sub-unit; the selection signal output sub-unit is configured to receive a source signal, and output a selection signal in accordance with the source signal; the selection sub-unit receives the selection signal and N clock signals, and outputs the received signal in accordance with the selection signal; and the clock signal input lines are no less than a number of N, and are configured to input the clock signals to the selection sub-unit, where N is an integer number which is higher than or equal to two. The gate driving structure of the GOA circuit, the array substrate and the display device occupies a small area. The driving method can achieve a single dot polarity inversion.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 18, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jiacheng Huang, Jian He, Xia Feng
  • Publication number: 20170098612
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Application
    Filed: December 16, 2016
    Publication date: April 6, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Publication number: 20170084526
    Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metallization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 9558958
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: January 31, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 9548240
    Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: January 17, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng