Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.

Abstract: A semiconductor device has a semiconductor die with an active surface. A first conductive layer is formed over the active surface. A first insulating layer is formed over the active surface. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second insulating layer is removed over the first conductive layer so that no portion of the second insulating layer overlies the first conductive layer. A second conductive layer is formed over the first conductive layer and first and second insulating layers. The second conductive layer extends over the first conductive layer up to the first insulating layer. Alternatively, the second conductive layer extends across the first conductive layer up to the first insulating layer on opposite sides of the first conductive layer. A third insulating layer is formed over the second conductive layer and first and second insulating layers.

Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Abstract: A method includes depositing a sacrificial material on a substrate, and depositing a polymer layer on the substrate and the sacrificial material. The method further includes removing the sacrificial material to at least partially define boundaries of at least one fluidic channel of a fluidic micro electromechanical system (MEM) device, the at least one fluidic channel is at least partially defined by a portion of the polymer layer and a portion of the substrate.

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract: A method includes depositing a sacrificial material on a substrate, and depositing a polymer layer on the substrate and the sacrificial material. The method further includes removing the sacrificial material to at least partially define boundaries of at least one fluidic channel of a fluidic micro electromechanical system (MEM) device, the at least one fluidic channel is at least partially defined by a portion of the polymer layer and a portion of the substrate.

Abstract: A fluidic micro electro-mechanical system (MEMS) device is described. In one aspect, at least one at least partially covered fluidic channel is formed between a polymer layer and a polymer substrate as the polymer layer is deposited on the substrate. The partially covered fluidic channel is fabricated as a unitary polymer layer structure. In one implementation, a strong exposure process is applied to the polymer layer to create a deep cross-linked polymer region. A weak exposure process is applied to the polymer layer to create a shallow cross-linked polymer region.

Abstract: A fluidic micro electro-mechanical system (MEMS) device is described. In one aspect, at least one at least partially covered fluidic channel is formed between a polymer layer and a polymer substrate as the polymer layer is deposited on the substrate. The partially covered fluidic channel is fabricated as a unitary polymer layer structure. In one implementation, a strong exposure process is applied to the polymer layer to create a deep cross-linked polymer region. A weak exposure process is applied to the polymer layer to create a shallow cross-linked polymer region.