Abstract: Certain aspects of the present disclosure generally relate to a high electron mobility transistor and techniques for fabricating the same. Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate; a channel region having a fin disposed above the substrate; a first barrier layer disposed adjacent to a first side and a second side of the first fin, wherein the first side and the second side of the first fin are opposite sides, the first barrier layer forming a heterojunction with the fin; a first dielectric layer disposed adjacent to a first side and a second side of the first barrier layer, wherein the first side and the second side of the first barrier layer are opposite sides; and a first gate region disposed adjacent to the first dielectric layer.

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis andY-axis dimensions of the horizontal footprint are reduced.

Abstract: A method, a device, and a non-transitory storage medium are described in which an island tracking area code detection and remedial service is provided. A device may detect an island tracking area code cell based on a predicted optimal tracking area code. The device calculates scores for neighbor cells and their corresponding tracking area codes based on the distances of the neighbor cells from a target cell. The device may select the predicted optimal tracking area code based on these scores. The device may use the predicted optimal tracking area code as a basis to determine whether a tracking area code assigned to the target cell is an island tracking area code cell. The device may perform a remedial measure when an island tracking area code cell is detected.

Abstract: The present invention relates in part to short-wave IR (SWIR) materials comprising generic mixed salts of empirical formula AaBbMcXd that are composition-dependent, broadband, and tunable. These materials have unique light absorbance wavelengths from 0.4 to 2.6 ?m, including both the visible and SWIR. The preparation procedure for the SWIR materials is simple, including the use of widely available, cheap, and non-toxic precursors, unlike existing state of the art alloy SWIR materials. These novel materials have broad applications in security, surveillance, military, machine vision, photovoltaic solar cells, medical treatments, spectroscopy detector, and thermography. The present invention also relates to methods of fabricating a film comprising the composition of the invention and to photovoltaic stacks comprising the composition of the invention.

Abstract: A horizontal gate-all-around (GAA) field effect transistor (FET) is described. The horizontal GAA FET includes a substrate as well as a shallow trench isolation (STI) region on the substrate. The horizontal GAA FET includes a first nano-sheet structure on the substrate and extending through the STI region. The first nano-sheet structure includes a first drain/source region stacked on a first source/drain region. The first nano-sheet structure also includes a first channel region between the first drain/source region and the first source/drain region. The horizontal GAA FET also includes a first gate on the STI region and horizontally surrounding the first channel region on four sides.

Abstract: A photo detector comprises a first photo diode configured to capture visible light, a second photo diode configured to capture one of infrared light or ultraviolet light, and an isolation region between the first photo diode and the second photo diode. The photo detector is capable of capturing infrared light and ultraviolet light in addition to visible light.

Abstract: A method, a device, and a non-transitory storage medium are described in which an island tracking area code detection and remedial service is provided. A device may detect an island tracking area code cell based on a predicted optimal tracking area code. The device calculates scores for neighbor cells and their corresponding tracking area codes based on the distances of the neighbor cells from a target cell. The device may select the predicted optimal tracking area code based on these scores. The device may use the predicted optimal tracking area code as a basis to determine whether a tracking area code assigned to the target cell is an island tracking area code cell. The device may perform a remedial measure when an island tracking area code cell is detected.

Abstract: Embodiments describe a display integration scheme in which an array of pixel driver chips embedded front side up in an insulator layer. A front side redistribution layer (RDL) spans across and is in electrical connection with the front sides of the array of pixel driver chips, and an array of light emitting diodes (LEDs) is bonded to the front side RDL. The pixel driver chips may be located directly beneath the display area of the display panel.

Abstract: The present disclosure relates to training one or more neural networks for vascular vessel assessment using synthetic image data for which ground-truth data is known. In certain implementations, the synthetic image data may be based in part, or derived from, clinical image data for which ground-truth data is not known or available. Neural networks trained in this manner may be used to perform one or more of vessel segmentation, decalcification, Hounsfield unit scoring, and/or estimation of a hemodynamic parameter.

Abstract: A transistor comprises a substrate, a first buffer layer on the substrate, a source region, a drain region, and a channel region on the first buffer layer, a gate on the channel region, a source contact, and a drain contact. The source contact is configured to contact at least three sides of the source region and the drain contact is configured to contact at least three sides of the drain region to lower contact resistance in the source region and in the drain region.

Abstract: A 3D vertically integrated FET for CMOS cell circuits is disclosed. Vertically integrating FETs for a 3D cell circuit reduces the footprint size of an IC chip. To reduce a CMOS cell circuit footprint, a PFET and an NFET are vertically integrated by stacking a second semiconductor layer including a second FET above a first semiconductor layer including a first FET, such that the channel structure of the second FET overlaps the channel structure of the first FET. The first FET may be an NFET, and the second FET may be a PFET, or vice versa. The longitudinal axis of the first FET channel structure may extend in a first plane parallel to a second plane including the longitudinal axis of the second FET channel structure. The longitudinal axes may be parallel or at an angle to each other, such that the second channel structure overlaps the first channel structure.

Abstract: A method, a device, and a non-transitory storage medium are described in which an island tracking area code detection and remedial service is provided. A device may detect an island tracking area code cell based on a predicted optimal tracking area code. The device calculates scores for neighbor cells and their corresponding tracking area codes based on the distances of the neighbor cells from a target cell. The device may select the predicted optimal tracking area code based on these scores. The device may use the predicted optimal tracking area code as a basis to determine whether a tracking area code assigned to the target cell is an island tracking area code cell. The device may perform a remedial measure when an island tracking area code cell is detected.

Abstract: A driving method for a display panel, a driving chip, and a display device are provided. The method includes: pre-storing Gamma curves corresponding to different display modes of the display panel; monitoring a display mode of the display panel when an image is displayed by the display panel, and acquiring a negative power voltage signal corresponding to the display mode; acquiring a Gamma curve corresponding to the display mode from the pre-stored Gamma curves based on the monitored display mode; outputting the negative power voltage signal to the display panel; and correcting the image displayed by the display panel according to the acquired Gamma curve. The above driving method is configured to drive the image displayed by the display panel.

Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.

Abstract: A heterojunction bipolar transistor (HBT) may include a base contact and emitter mesas on a collector mesa. The HBT may include emitter contacts on the emitter mesas. The HBT may include a first dielectric layer on the collector mesa, sidewalls of the emitter mesas, and the base contact. The HBT may further include a second dielectric layer on the first dielectric layer and on sidewalls of the emitter contacts. The HBT may further include a secondary conductive layer on the first dielectric layer, the second dielectric layer, and the emitter contacts.

Abstract: Certain aspects of the present disclosure provide a variable transistor-based capacitive element implemented on a glass or dielectric substrate. Such a variable transistor-based capacitive element may be suitable for use as a tunable capacitor in a passive-on-glass (POG) device, for example. One example device having a tunable capacitance generally includes a glass or dielectric substrate and a transistor disposed above the glass or dielectric substrate. The transistor has a gate region, a drain region, and a source region, wherein a capacitance of the transistor is configured to vary based on a voltage between the gate region and the drain region.

Abstract: A variable capacitor includes a mesa on a substrate. The mesa has multiple III-V semiconductor layers and includes a first side and a second side opposite the first side. The first side has a first sloped portion and a first horizontal portion. The second side has a second sloped portion and a second horizontal portion. A control terminal is on a third side of the mesa. A first terminal is on the first side of the mesa. The first terminal is disposed on the first horizontal portion and the first sloped portion. A second terminal is also on the substrate.

Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.

Abstract: In certain aspects, an apparatus comprises a plurality of PUF cells. Each PUF cell comprises a first transistor in series with a first loading resistive component and coupled to a common cross-coupled node and cross-coupled to a complementary common cross-coupled node, a second transistor in series with a second loading resistive component and coupled to the complementary common cross-coupled node and cross-coupled to the common cross-coupled node, a first pass-gate and a second pass-gate coupled to a bit line and the complementary bit line, respectively. The apparatus further comprises an auxiliary peripheral circuit coupled to the bit line, the complementary bit line, the common cross-coupled node, and the complementary common cross-coupled node. During activation, the selected PUF cell, together with the auxiliary peripheral circuit, forms a cross-coupled inverter pair and outputs a physical unclonable function value.