Abstract: The present disclosure is directed to methods of making Pb-free perovskites for short-wave IR (SWIR) devices and to various Pb-free perovskite materials disclosed herein. The perovskites disclosed herein have improved chemical stability and long-term stability, while the production methods disclosed herein have improved safety and lower cost.

Abstract: All inorganic perovskites for short-wave IR (SWIR) devices having improved chemical stability and long-term stability. Improved methods of making all inorganic perovskites for short-wave IR (SWIR) devices are also disclosed herein.

Abstract: A device may receive input data associated with a wireless network, and may extract data from the input data to generate extracted data. The device may create PRB images based on the extracted data, and may process the PRB images, with a first model, to associate labels with each of the PRB images. The device may process the labels and the PRB images, with a second model, to identify potential issues associated with the PRB images, and may process data identifying the potential issues associated with the PRB images, with a third model, to compress the data identifying the potential issues into an array. The device may process the array, with a fourth model, to determine probability scores associated with the potential issues, and may select a potential issue with a greatest probability score as a detected issue. The device may perform actions based on the detected issue.

Abstract: The invention discloses a device for producing biogas with high methane content by utilizing livestock and poultry feces, wherein the interior of a tank body of a biogas fermentation tank is divided by a baffle, so as to form a main reaction chamber and an auxiliary reaction chamber which are communicated in upper portions, so that a reactant flows into the auxiliary reaction chamber only after entering the main reaction chamber via a relatively low feeding hole and then reaching a high position of a liquid level, and extension of fermentation time is realized, meanwhile, scales formed at the top of fermentation broth flow into the auxiliary reaction chamber along with liquid, so that the interior of the main reaction chamber keeps a liquid state all the time, and sealing and reduction of quantity of anaerobic bacteria are avoided.

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a ferroelectric (FE) semiconductor device having a channel region; a gate oxide; a FE region, wherein the gate oxide is disposed between the FE region and the channel region; a gate region, wherein the FE region is disposed between the gate oxide and the gate region; a first semiconductor region disposed adjacent to the channel region; and a second semiconductor region disposed adjacent to the channel region. The semiconductor device may also include a transistor, wherein a region of the transistor is connected to the gate region, the first semiconductor region, or the second semiconductor region of the FE semiconductor device.

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.

Abstract: The present disclosure provides a compound having a structure represented by Formula 1, where X1-X4 are each independently selected from a carbon atom or a nitrogen atom, and at least two of X1-X4 are each a nitrogen atom; R1-R4 are independently absent or selected from hydrogen, C1-C20 alkyl, C1-C20 alkoxy, C1-C20 alkylthio, C1-C20 alkylamino, C6-C30 aryl, or C2-C30 heteroaryl; m is 1 or 2; n and q are each independently selected from 0, 1, or 2, n+q?1, and m+n+q=3; Ar is C6-C30 aryl. The molecular structure of the compound has a nitrogen-containing multidentate ligand suitable to form complexes with metal Yb or LiQ to form a metal organic complex having multidentate bondings. When applied to an OLED device, it can effectively lower the turn-on voltage and operating voltage, improve the efficiency, and prolong lifetime of the OLED device.

Abstract: Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

Abstract: Circuits employing on-diffusion (OD) edge (ODE) dummy gate structures in cell circuit with increased gate dielectric thickness to reduce leakage current are disclosed. A gate dielectric structure may be formed between a work function metal structure of an ODE dummy gate structure and an active semiconductor structure in a cell circuit, and is provided to be thicker than a gate dielectric structure formed between a work function metal structure and an active gate(s) in the cell circuit. Providing a gate dielectric structure of increased thickness can reduce damage to the gate dielectric structure providing isolation between the ODE dummy gate structure and the active semiconductor structure. Providing a gate dielectric structure of increased thickness can also reduce the gap area adjacent to the ends of the active semiconductor structures and thus reduce the volume of work function metal structure formed in the gaps to further reduce leakage current.

Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

Abstract: The present disclosure belongs to technical field of OLEDs, and provides a compound suitable as a hole transport material and an electron blocking material of OLEDs. The compound has a general structure according to [Chemical Formula 1], in which Ar1 and Ar2 are each independently selected from a hydrogen atom, a substituted or unsubstituted C5-C40 aryl, or a substituted or unsubstituted C5-C40 heteroaryl; m and n are each an integer independently selected from 0, 1, or 2; X is selected from O, S, or —NR—; R is selected from hydrogen, or a substituted or unsubstituted C5-C40 aryl; Ar3 has a structure according to [Chemical Formula 2], in which R1-R8 are each independently selected from a hydrogen atom, or a substituted or unsubstituted C5-C40 aryl; Y is selected from O, S, or —NR?—; and R? is selected from a hydrogen atom, or a substituted or unsubstituted C5-C40 aryl.

Abstract: Certain aspects of the present disclosure generally relate to a vertical resistive random access memory (RRAM). The vertical RRAM generally includes a planar substrate layer and a plurality of fin-like metal-insulator-metal (MIM) structures extending orthogonally above the substrate layer.

Abstract: The present disclosure relates to training one or more neural networks for vascular vessel assessment using synthetic image data for which ground-truth data is known. In certain implementations, the synthetic image data may be based in part, or derived from, clinical image data for which ground-truth data is not known or available. Neural networks trained in this manner may be used to perform one or more of vessel segmentation, decalcification, Hounsfield unit scoring, and/or estimation of a hemodynamic parameter.

Abstract: A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

Abstract: A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.

Abstract: Hybrid chiplets, display backplanes, and displays with integrated hybrid chiplets are described. In an embodiment, a hybrid chiplet includes a micro LED chiplet stacked on a micro driver chiplet that includes at least one drive transistor and a bottom side including a plurality of bottom chiplet contacts for electrical connection with a display backplane.

Abstract: Certain aspects of the present disclosure provide apparatus for thermal matching of integrated circuits (ICs). One example apparatus generally includes a first substrate, a first IC disposed on the first substrate and having a second substrate, and a second IC disposed on the first substrate. The second IC may include a third substrate, a thermal conductivity adjustment region comprising different material than the third substrate, the thermal conductivity adjustment region being adjacent to a first side of the third substrate, and one or more electrical components formed in one or more layers of the second IC adjacent to a second side of the third substrate, wherein the first side and the second side are opposite sides of the third substrate, and wherein a thermal conductivity of the thermal conductivity adjustment region is closer to a thermal conductivity of the second substrate than a thermal conductivity of the third substrate.

Abstract: In an embodiment, a power switch controller for driving a back-to-back power switch includes: an amplifier having a supply terminal configured to receive a supply voltage, an output configured to be coupled to a gate terminal of the back-to-back power switch, a first input configured to be coupled a source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier. The amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier.

Abstract: A simple approach to produce mixed Cu/Cu2O nanocrystals having a specific morphology by controlling the reaction temperature during Cu/Cu2O nanocrystals synthesis. Other variables are kept constant, such as the amount of reactants, while the reaction temperatures is maintained at a predetermined temperature of 70° C., 30° C. or 0° C., which are used to produce different and controlled morphologies for the Cu/Cu2O nanocrystals. The reaction mixture includes a copper ion contributor, a capping agent, a pH adjustor, and reducing agent. The reaction mixture is held at the predetermined temperature for three hours to produce the Cu/Cu2O nanocrystals. The synthesis method has advantages such as mass production, easy operation, and high reproducibility.