Abstract: A method of manufacturing a vertical metal-insulator-metal capacitor (MIMCap) (10) in regions (19) of an insulating layer (14). Trenches for both conductive lines and vertical MIMCap's are formed in the insulating layer (14), and regions (19) are covered by resist (20) while the conductive lines (24) are deposited on the wafer. The resist (20) is removed, and the MIMCap dielectric and top plate conductive material (28) is deposited, forming a vertical MIMCap in regions (19).

Abstract: A parallel capacitor structure that can be fabricated using advanced processing techniques that employ, for example, copper interconnects and low k dielectrics is described. The parallel capacitor structure includes a first copper dual Damascene interconnection line, a first interconnection, a middle capacitor electrode, a dielectric layer, a second interconnection, an upper capacitor electrode, and a second interlayer dielectric layer. The existing first copper dual Damascene interconnection line is embedded in a first interlayer dielectric layer, and is utilized as a lower capacitor electrode. The middle capacitor electrode is on the first copper dual Damascene interconnection line. The dielectric layer is interposed between the first copper dual Damascene interconnection line and the middle capacitor electrode. The second interconnection can be directly connected to the middle capacitor electrode.

Abstract: A method of fabricating an MRAM device includes patterning a magnetic stack material layer (142) using a hard mask (146) formed by a “plate-through” technique. A resist (144) is deposited over magnetic stack material (142), and the resist (144) is patterned, exposing regions of the magnetic stack material (142). A hard mask (146) is formed over the magnetic stack material (142) exposed regions through the resist (144), and the hard mask (146) is used to pattern magnetic tunnel junctions (MJT's) of the MRAM device. Electroplating, electro-less plating, sputtering, physical vapor deposition (PVD), evaporation deposition, or combinations thereof are used to deposit a material comprising a metal over the magnetic stack material (142) exposed regions to form the hard mask (146).

Abstract: A method of manufacturing a metal-insulator-metal capacitor (MIMCap) (36) including first conductive lines (15), capacitor dielectric (26) and second conductive lines (28), the MIMCap (36) including horizontal capacitive portions (32) and vertical capacitive portions (34). The method includes forming first conductive lines (15) in a first insulating layer (14) of a wafer (10), depositing a second insulating layer (22), depositing a resist, removing portions of the resist, removing exposed portions of the second insulating layer (22) and portions of the first insulating layer (14), removing the remaining resist, and then depositing a capacitor dielectric (26) and second conductive lines (28).

Abstract: A method of forming a metal-insulator-metal capacitor (see e.g., FIG. 1) in a back end of line structure comprises forming a metal bottom plate 16 in a first metalization layer 14, sputter depositing a high dielectric constant material 18 over the bottom plate 16, and forming a metal top plate 20 in a second metalization layer 22. The metal bottom plate 16 and metal top plate 22 are formed in consecutive metalization layers 14 and 22 in which interconnect structures 12 and 24 are also formed.

Abstract: A method of preparing a stacked metal-insulation-metal capacitor (MIMCap) in between Cu dual-damascene levels in a process of forming a semiconductor wafer to enable doubling of the capacitor's capacitance without the additional process steps utilized when an MIMCap is built in a Cu damascene level using Cu as a bottom plate and a top plate patterned on top of the dielectric, comprising:

Abstract: A method of forming MIM capacitor top (16) and bottom (12) plates, using a first and second resist (18/20) and a single RIE process. A first conductive layer (12) is deposited over a substrate (10). An insulating layer (14) is deposited over the first conductive layer (12). A second conductive layer (16) is deposited over the insulating layer (14). A first resist (18) is deposited over the second conductive layer (16), and the first resist (18) is patterned. A second resist (20) is deposited over the first resist (18) and patterned. The first and second resist (18/20) patterns are simultaneously transferred to the first and second conductive layers (12) and (16), respectively, by exposure to a single reactive ion etch (RIE) process.

Abstract: A method for making a metal-insulator-metal capacitive structure includes depositing a copper barrier and seed layer over a support structure such as an inter-level dielectric layer, forming a dielectric over the copper barrier and seed layer, and then forming a forming a metal layer over the dielectric. The copper barrier and seed layer forms a bottom plate of a capacitor, and the metal layer forms the upper plate which is separated from the bottom plate by the dielectric. By forming the bottom plate from a copper barrier and seed layer, reduced sheet resistance and surface roughness is achieved, both of which enhance the performance of the capacitor. This performance is further enhanced by forming the capacitor to have a damascene structure. Preferably, at least one conductive interconnect is formed simultaneously with the formation of the capacitor. This is made possible, at least in part, by forming the interconnect using a plate-through mask technique.

Abstract: A vertical MIM capacitor (140) including a first conductive line (124) and second conductive line (136) sandwiched around a vertical portion of a capacitor dielectric (134). Additional conductive lines (136) may be positioned vertically proximate first conductive lines (124) separated by another vertical portion of capacitor dielectric (134) to form a double-sided capacitor (142), increasing the capacitance. A plurality of vertical MIMcaps (140, 142) may be coupled together in parallel to increase the capacitance.

Abstract: A method of patterning conductive lines (252) of a memory array integrated circuit (200) using a hard mask (244) and reactive ion etching (RIE). Using a hard mask (244) prevents oxidation of underlying conductive lines (210).

Abstract: memory array integrated circuit (200) using a hard mask (244) and reactive ion etching (RIE). Using a hard mask (244) prevents oxidation of underlying conductive lines (210).

Abstract: Method of forming a magnetic memory device are disclosed. In one embodiment, a first plurality of conductive lines are formed over a semiconductor workpiece. A plurality of magnetic material lines are formed over corresponding ones of the first plurality of conductive lines and a second plurality of conductive lines are formed over the semiconductor workpiece. The second plurality of conductive lines cross over the first conductive lines and the magnetic material lines. These second lines can be used as a mask to while the magnetic material lines are patterned.

Abstract: An MRAM device (160) and manufacturing process thereof having aluminum conductive lines (134) and (152), with self-aligning cross-points. Conductive lines (134) and metal stack (138) are patterned in a single patterning step and etched. Conductive lines (152) positioned orthogonally to conductive lines (134) are patterned simultaneously with the patterning of metal stack (138) and are etched. The metal stack (138) serves as an anti-reflective coating for conductive lines (152) during the etching process. A multi-level MRAM device may be manufactured in accordance with an embodiment of the invention.

Abstract: A semiconductor device (100) having a copper damascene BEOL structure. A metal cap layer (120) is formed over conductive lines (118) to prevent oxidation of the conductive lines (118) during subsequent processing steps. The metal cap layer (120) comprises a material other than the conductive line (118) material that is resistant to oxidation. The structure (100) is particularly beneficial for MRAM devices.

Abstract: A method for producing a semiconductor device having an alignment mark, the method comprising forming a first dielectric layer within which a trench having predetermined dimensions is etched and depositing a first layer of metal into the trench; forming a second dielectric layer over the first dielectric layer and over the first layer of metal; simultaneously etching lines and an opening into the second dielectric layer, at least one line used as a via extending to the first layer of metal; filling the lines and the opening, the filling controlled to fill the lines and to under fill the opening; performing chemical mechanical polishing of the plate; and depositing a non-transparent stack of layers onto the metal, whereby the non-transparent stack of layers conforms to the surface of the under filled opening resulting in an alignment mark on the non-transparent stack of layers in order to align successive layers.

Abstract: A vertical MIM capacitor (140) including a first conductive line (124) and second conductive line (136) sandwiched around a vertical portion of a capacitor dielectric (134). Additional conductive lines (136) may be positioned vertically proximate first conductive lines (124) separated by another vertical portion of capacitor dielectric (134) to form a double-sided capacitor (142), increasing the capacitance. A plurality of vertical MIMcaps (140, 142) may be coupled together in parallel to increase the capacitance.

Abstract: An all dry, low temperature process, for complete removal of organics and inorganic residues after metal etch of a microelectronic device comprising: rinsing a microelectronic device having a metallization layer after metal etch with a solution of ammonium hydroxide and hydrogen peroxide; subjecting the rinsed metallization layer to a low temperature GaSonics cleaning by exposing photoresist residue surface of the metallization layer to a fluorine containing reactive gas to form volatile compounds in the presence of a radio frequency input followed by photoresist stripping in an oxygen plasma at low temperature; subjecting the low temperature GaSonics treated residue surface to a gaseous SO3 strip at low temperature to remove additional residue; and rinsing the SO3 stripped material with de-ionized water to remove any remaining resist and residue.

Abstract: An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).

Abstract: Methods for detecting under-etched vias, spaces, or under-polished portions in a wafer stack are disclosed. The wafer stack comprises a dielectric layer disposed on a metal layer. The dielectric layer has a plurality of vias etched therein. The wafer stack, including the plurality of vias, is exposed to an etchant which is configured to etch the metal layer at a substantially faster rate than the dielectric layer. As a result, cavities are formed in the metal layer below properly-etched vias. Then, the vias in the wafer stack are optically inspected to detect and identify under-etched vias, which reflect more light than the cavities etched into the metal layer.

Abstract: A substrate cleaning assembly (10) and method for removing contaminant substances (11) from a surface (12) of a substrate (13) employed in microelectronics manufacturing. The cleaning assembly (10) includes a substance locator (15) adapted to locate and map at least one contaminant substance (11) on the surface (12) of the substrate (13) and a dispenser (16) formed and dimensioned to accurately dispense a substantially controlled, impinging stream (17) of cleaning agent along a path (18). A controller (20) is coupled to the map device (15) and the dispenser (16), and is adapted to control the impinging stream (17) such that the located contaminant substance (11) is positioned in the path (18) of the impinging stream (17) to enable substantially localized impingement and removal of the substance (11) from the substrate surface (12).