Abstract: A gas extraction device for metal mineral inclusions and a gas extraction method therefor are provided, the device includes a base plate, an annular carrier, sealing covers, a grinding assembly, a vacuum assembly, a gas-gathering assembly and a mass spectrometer. The annular carrier is disposed on the base plate, multiple grinding chambers are defined and evenly distributed in a circular shape on the annular carrier, the sealing covers are disposed at openings of the grinding chambers, the grinding assembly includes grinding hammers, and the grinding hammers penetrate through the sealing covers and extend into the grinding chambers. Side walls of each grinding chamber defines a first through hole and a second through hole. The vacuum assembly is communicated with the grinding chambers through the first through holes. The gas-gathering assembly is communicated with the grinding chambers through the second through holes. The mass spectrometer is communicated with the gas-gathering assembly.

Abstract: A keyboard device includes a key module and a backlight module. The key module includes a supporting plate and plural key structures. The key structures are installed on the supporting plate. The backlight module includes a light guide plate, a light-sheltering layer, a reflecting layer, a light-emitting unit, a base plate and an opaque structure. The light guide plate includes a second opening. The second opening includes a lateral wall. The light-sheltering layer is located over the light guide plate. The light-sheltering layer includes a third opening. The reflecting layer is located under the light guide plate. The reflecting layer includes a fourth opening. The light-emitting unit emits a light beam into the light guide plate. The opaque structure is arranged between the light-sheltering layer and the reflecting layer. The opaque structure is located beside the lateral wall of the light guide plate.

Abstract: An imaging system lens assembly includes, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The second lens element with positive refractive power has an image-side surface being convex in a paraxial region thereof. The third lens element has an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof. The fifth lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof and having at least one inflection point.

Abstract: Methods for input/output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

Abstract: The present invention discloses a method for calibrating controllable phase shifters in a multi-stage staggered Mach-Zehnder interferometer structure on an optical chip, aiming to solve the problem of calibrating the controllable phase shifters in a configurable optical network of the multi-stage staggered Mach-Zehnder interferometers. The technical solution is to calibrate the controllable phase shifters that can be calibrated in the optical network; and then to constitute calibration conditions for and calibrate inner phase shifters that has not been; and finally to constitute calibration conditions for and calibrate outer phase shifters that is not calibrated.

Abstract: A photographing optical lens assembly includes five lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has positive refractive power. The second lens element has negative refractive power. When specific conditions are satisfied, the requirements of compact size and high image quality can be met by the photographing optical lens assembly, simultaneously.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: An imaging system lens assembly includes six lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The third lens element has negative refractive power. At least one surface of at least one of the first lens element to the sixth lens element includes at least one inflection point.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A controller includes memory and a microcontroller coupled to the memory. The memory is configured to store a list of entries of data in Flash memory coupled to the controller. The microcontroller is configured to periodically update the list of entries based on data programmed into the Flash memory, and check the list of entries upon reading data from the Flash memory.

Abstract: A memory device includes a string of cells having one and more top selection cells, one or more dummy memory cells, and memory cells, and a peripheral circuit coupled to the string of cells. The peripheral circuit is configured to verify a threshold voltage of at least one of the one or more top selection cells or the one or more dummy memory cells to determine whether the at least one of the one or more top selection cells or the one or more dummy memory cells has failed. In response to the at least one of the one or more top selection cells or the one or more dummy memory cells being failed, the peripheral circuit is further configured to reset the at least one of the one or more top selection cells or the one or more dummy memory cells.

Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

Abstract: Techniques for encoding video with reduced frame-boundary artifacts are presented. The techniques include a video encoding method, where, when skip mode is selected as a motion prediction coding mode for a pixel block predicted from a reference block of a reference frame, estimating an amount of the reference block that extends beyond the edge of the reference frame. If the amount beyond the edge does not exceed a threshold, the prediction may be coded with skip mode. If the amount beyond the edge exceeds a threshold, the pixel block may be partitioned, and the partitioned blocks may be coded with motion prediction.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A controller includes memory and a microcontroller coupled to the memory. The memory is configured to store a list of entries of data in Flash memory coupled to the controller. The microcontroller is configured to periodically update the list of entries based on data programmed into the Flash memory, and check the list of entries upon reading data from the Flash memory.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

Abstract: An electronic apparatus including flash memory and a flash controller is provided. The flash controller is coupled to the flash memory and used to manage data access to the flash memory. The flash controller includes a timer, memory and a microcontroller coupled to the timer and the memory. The timer is used to generate clock interrupts. The memory is used to retain for a predetermined period of time a list of entries of data programmed into the flash memory. Upon each clock interrupt, the microcontroller is used to write an entry of data being programmed into the flash memory to update the list of entries.

Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.