Patents by Inventor Xiang Fu
Xiang Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250216282Abstract: A device for cavitation monitoring of a hydraulic system includes a branch pipe connected to a hydraulic pipe; a movable unit arranged in the branch pipe and in sliding fit with the branch pipe; and an acquisition unit arranged in the branch pipe and configured to acquire position information of the movable unit. The movable unit is configured such that when a gas filling amount in a medium in the hydraulic pipe changes, the movable unit moves along the branch pipe. The device also includes an information display unit connected to the acquisition unit and configured to analyze and display the position information acquired by the acquisition unit. The device also includes a buffer unit connected to one side of the movable unit close to the hydraulic pipe.Type: ApplicationFiled: January 15, 2025Publication date: July 3, 2025Inventors: Qiang ZHANG, Yang WANG, Ying TIAN, Shouji SUN, Chunyong FAN, Hengxuan LUAN, Feng ZHOU, Dongliang WEI, Li YIN, Hong ZHANG, Bofeng CHANG, Xin LIU, Chenglong WANG, Ya LIU, Chao ZHANG, Yongrui YANG, Xiang FU
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Publication number: 20250156692Abstract: Examples are disclosed that relate to a generative model for generating inorganic material candidates, such as crystalline structures. One example provides a method, comprising training an unconditional generative model using a dataset of stable periodic material structures, the unconditional generative model comprising a diffusion model. The training comprises learning the diffusion model to iteratively noise the stable periodic material structures of the dataset towards a random periodic structure by noising atom types of atoms in the periodic material structure, noising fractional coordinates of the atoms in the periodic material structure, and noising a lattice of the periodic material structure. The method further comprises using the trained unconditional generative model to generate a material structure by iteratively denoising an initial structure sampled from a random distribution.Type: ApplicationFiled: June 28, 2024Publication date: May 15, 2025Applicant: Microsoft Technology Licensing, LLCInventors: Tian XIE, Andrew Thomas FOWLER, Claudio ZENI, Daniel ZUEGNER, Robert PINSLER, Ryota TOMIOKA, Matthew Kristofer HORTON, Xiang FU
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Publication number: 20250123465Abstract: An optical imaging lens assembly includes nine lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element, an eighth lens element and a ninth lens element. The first lens element has negative refractive power. The second lens element with negative refractive power has an object-side surface being convex and an image-side surface being concave in a paraxial region thereof. The fourth lens element has an image-side surface being convex in a paraxial region thereof. The fifth lens element has positive refractive power. The sixth lens element has an image-side surface being concave in a paraxial region thereof. The eighth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof.Type: ApplicationFiled: November 21, 2023Publication date: April 17, 2025Applicant: LARGAN PRECISION CO., LTD.Inventors: Wei-Xiang FU, Yu-Chun KE, Cheng-Yu TSAI
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Patent number: 12272410Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).Type: GrantFiled: February 10, 2023Date of Patent: April 8, 2025Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zilong Chen, Xiang Fu
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Publication number: 20250078941Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).Type: ApplicationFiled: November 14, 2024Publication date: March 6, 2025Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zilong CHEN, Xiang FU
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Patent number: 12142327Abstract: A memory device includes a string of cells having one and more top selection cells, one or more dummy memory cells, and memory cells, and a peripheral circuit coupled to the string of cells. The peripheral circuit is configured to verify a threshold voltage of at least one of the one or more top selection cells or the one or more dummy memory cells to determine whether the at least one of the one or more top selection cells or the one or more dummy memory cells has failed. In response to the at least one of the one or more top selection cells or the one or more dummy memory cells being failed, the peripheral circuit is further configured to reset the at least one of the one or more top selection cells or the one or more dummy memory cells.Type: GrantFiled: June 30, 2022Date of Patent: November 12, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Qiang Tang, Xiang Fu
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Publication number: 20240085664Abstract: An imaging system lens assembly includes, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The second lens element with positive refractive power has an image-side surface being convex in a paraxial region thereof. The third lens element has an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof. The fifth lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof and having at least one inflection point.Type: ApplicationFiled: October 5, 2022Publication date: March 14, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Wei-Xiang FU, Jin Sen WANG, I-Hsuan CHEN, Hsin-Hsuan HUANG
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Publication number: 20240079054Abstract: Methods for input/output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Shiyang YANG, Chunfei Deng, Yan Lu, Ling Ding, Xiang Fu
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Patent number: 11892742Abstract: The present invention discloses a method for calibrating controllable phase shifters in a multi-stage staggered Mach-Zehnder interferometer structure on an optical chip, aiming to solve the problem of calibrating the controllable phase shifters in a configurable optical network of the multi-stage staggered Mach-Zehnder interferometers. The technical solution is to calibrate the controllable phase shifters that can be calibrated in the optical network; and then to constitute calibration conditions for and calibrate inner phase shifters that has not been; and finally to constitute calibration conditions for and calibrate outer phase shifters that is not calibrated.Type: GrantFiled: September 10, 2020Date of Patent: February 6, 2024Assignee: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGYInventors: Junjie Wu, Yang Wang, Xiaogang Qiang, Ping Xu, Jiangfang Ding, Mingtang Deng, Anqi Huang, Xiang Fu
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Publication number: 20240012223Abstract: A photographing optical lens assembly includes five lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has positive refractive power. The second lens element has negative refractive power. When specific conditions are satisfied, the requirements of compact size and high image quality can be met by the photographing optical lens assembly, simultaneously.Type: ApplicationFiled: August 31, 2022Publication date: January 11, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Yu Jui LIN, Yu-Tai TSENG, Wei-Xiang FU, Cheng-Yu TSAI, Hsin-Hsuan HUANG
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Publication number: 20230197170Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).Type: ApplicationFiled: February 10, 2023Publication date: June 22, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zilong CHEN, Xiang FU
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Publication number: 20230121630Abstract: An imaging system lens assembly includes six lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The third lens element has negative refractive power. At least one surface of at least one of the first lens element to the sixth lens element includes at least one inflection point.Type: ApplicationFiled: September 16, 2022Publication date: April 20, 2023Inventors: Wei-Xiang FU, Hsin-Hsuan HUANG, Meng-Kuan CHO
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Patent number: 11600342Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).Type: GrantFiled: May 19, 2021Date of Patent: March 7, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zilong Chen, Xiang Fu
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Patent number: 11567701Abstract: A controller includes memory and a microcontroller coupled to the memory. The memory is configured to store a list of entries of data in Flash memory coupled to the controller. The microcontroller is configured to periodically update the list of entries based on data programmed into the Flash memory, and check the list of entries upon reading data from the Flash memory.Type: GrantFiled: April 21, 2021Date of Patent: January 31, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Huang Peng Zhang, Xiang Fu, Qi Wang
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Publication number: 20220336026Abstract: A memory device includes a string of cells having one and more top selection cells, one or more dummy memory cells, and memory cells, and a peripheral circuit coupled to the string of cells. The peripheral circuit is configured to verify a threshold voltage of at least one of the one or more top selection cells or the one or more dummy memory cells to determine whether the at least one of the one or more top selection cells or the one or more dummy memory cells has failed. In response to the at least one of the one or more top selection cells or the one or more dummy memory cells being failed, the peripheral circuit is further configured to reset the at least one of the one or more top selection cells or the one or more dummy memory cells.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Qiang Tang, Xiang Fu
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Patent number: 11393544Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.Type: GrantFiled: February 26, 2021Date of Patent: July 19, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Qiang Tang, Xiang Fu
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Patent number: 11140407Abstract: Techniques for encoding video with reduced frame-boundary artifacts are presented. The techniques include a video encoding method, where, when skip mode is selected as a motion prediction coding mode for a pixel block predicted from a reference block of a reference frame, estimating an amount of the reference block that extends beyond the edge of the reference frame. If the amount beyond the edge does not exceed a threshold, the prediction may be coded with skip mode. If the amount beyond the edge exceeds a threshold, the pixel block may be partitioned, and the partitioned blocks may be coded with motion prediction.Type: GrantFiled: December 17, 2018Date of Patent: October 5, 2021Inventors: Xiang Fu, Xiaohua Yang, Linfeng Guo, Francesco Iacopino, Felix Chou, Ying Jian He
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Publication number: 20210272637Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zilong CHEN, Xiang FU
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Publication number: 20210240397Abstract: A controller includes memory and a microcontroller coupled to the memory. The memory is configured to store a list of entries of data in Flash memory coupled to the controller. The microcontroller is configured to periodically update the list of entries based on data programmed into the Flash memory, and check the list of entries upon reading data from the Flash memory.Type: ApplicationFiled: April 21, 2021Publication date: August 5, 2021Inventors: Huang Peng Zhang, Xiang Fu, Qi Wang
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Patent number: 11043279Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).Type: GrantFiled: December 30, 2019Date of Patent: June 22, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zilong Chen, Xiang Fu