Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

Abstract: An electronic apparatus including flash memory and a flash controller is provided. The flash controller is coupled to the flash memory and used to manage data access to the flash memory. The flash controller includes a timer, memory and a microcontroller coupled to the timer and the memory. The timer is used to generate clock interrupts. The memory is used to retain for a predetermined period of time a list of entries of data programmed into the flash memory. Upon each clock interrupt, the microcontroller is used to write an entry of data being programmed into the flash memory to update the list of entries.

Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: The present invention discloses a method for calibrating controllable phase shifters in a multi-stage staggered Mach-Zehnder interferometer structure on an optical chip, aiming to solve the problem of calibrating the controllable phase shifters in a configurable optical network of the multi-stage staggered Mach-Zehnder interferometers. The technical solution is to calibrate the controllable phase shifters that can be calibrated in the optical network; and then to constitute calibration conditions for and calibrate inner phase shifters that has not been; and finally to constitute calibration conditions for and calibrate outer phase shifters that is not calibrated.

Abstract: An electronic apparatus including flash memory and a flash controller is provided. The flash controller is coupled to the flash memory and used to manage data access to the flash memory. The flash controller includes a timer, memory and a microcontroller coupled to the timer and the memory. The timer is used to generate clock interrupts. The memory is used to retain for a predetermined period of time a list of entries of data programmed into the flash memory. Upon each clock interrupt, the microcontroller is used to write an entry of data being programmed into the flash memory to update the list of entries.

Abstract: A memory control system includes a memory interface, a microcontroller, and a sequence processing unit. The memory interface circuit receives a memory operation command and generates a plurality of operation instructions according to the memory operation command. The microcontroller is coupled to the memory interface circuit . The microcontroller receives the plurality of operation instructions and generates a plurality of task instructions according a scheduling algorithm through a predetermined protocol. The sequence processing unit is coupled to the microcontroller. The sequence processing unit receives the plurality of task instructions through the predetermined protocol, and controls a plurality of circuits of a memory device according to the plurality of task instructions with at least one finite state machine of the sequence processing unit.

Abstract: Techniques are disclosed for coding image data adaptively at different levels of downscaling. Such techniques may involve partitioning input data into pixel blocks for coding and performing content analysis on the pixel blocks. The pixel blocks may be input to block coders that operate at different pixel block sizes, which may code the pixel blocks input to them at their respective sizes. Except when a block coder operates at the partitioning size, block coders that operate at different pixel block sizes may perform downscaling of the pixel blocks to match their size with the block coders' respective coding size. A block decoder may invert the coding operations performed by the block coders, decoding coded image data at respective pixel block sizes, then upscaling decoded image data obtained therefrom to a common pixel block size. Image reconstruction may synthesize a resultant image from the decode pixel block data output by the decoders.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.

Abstract: The present invention provides a data processing method for a memory and a related data processor for performing the method. A page of data may be divided into multiple groups. In each group, the number of “1”s and the number of “0”s are determined, so as to determine whether to reverse or keep the bit data in the group. The encoding scheme may make the bit value “0” more concentrated on the middle states of the state distribution than the bit value “1”. The data processor thereby reverses the bit data in a group if the number of “1”s is greater than the number of “0”s in the group, and keeps the bit data in a group if the number of “1”s is less than the number of “0”s in the group. As a result, the occurrence probability of the states at two sides becomes lower and the occurrence probability of the middle states becomes higher. This improves data retention of the memory.

Abstract: Systems and methods are disclosed for improving the quality of a reconstructed video sequence that was captured under low light conditions by means of bitrate budget management. In response to a low illumination video capture detection, and based on estimation of the video image characteristics, frame bitrate budget and/or frame rate, used in motion compensated predictive coding techniques, are modified from their default values.

Abstract: Techniques are disclosed for developing quantization matrices for use in video coding. According to these techniques a first quantization matrix may be derived from a second quantization matrix by scaling quantization values of the second quantization matrix by scaling parameters. The scaling parameters may increase according to distance between each matrix position and a matrix origin, they may be derived from characteristics of a video sequence to be coded, or both. The first quantization matrix may be communicated to a decoder. Thereafter, a video sequence may be coded predictively. As part of the coding, pixel data of the video sequence may be transformed to a plurality of frequency domain coefficients, and the frequency domain coefficients may be quantized according to the first quantization matrix.

Abstract: Techniques are disclosed for coding image data adaptively at different levels of downscaling. Such techniques may involve partitioning input data into pixel blocks for coding and performing content analysis on the pixel blocks. The pixel blocks may be input to block coders that operate at different pixel block sizes, which may code the pixel blocks input to them at their respective sizes. Except when a block coder operates at the partitioning size, block coders that operate at different pixel block sizes may perform downscaling of the pixel blocks to match their size with the block coders' respective coding size. A block decoder may invert the coding operations performed by the block coders, decoding coded image data at respective pixel block sizes, then upscaling decoded image data obtained therefrom to a common pixel block size. Image reconstruction may synthesize a resultant image from the decode pixel block data output by the decoders.

Abstract: Techniques for encoding video with reduced frame-boundary artifacts are presented. The techniques include a video encoding method, where, when skip mode is selected as a motion prediction coding mode for a pixel block predicted from a reference block of a reference frame, estimating an amount of the reference block that extends beyond the edge of the reference frame. If the amount beyond the edge does not exceed a threshold, the prediction may be coded with skip mode. If the amount beyond the edge exceeds a threshold, the pixel block may be partitioned, and the partitioned blocks may be coded with motion prediction.

Abstract: The present invention relates to an occluder, comprising a meshed occlusion body provided with a cavity, and a proximal hub, as well as a locking member and a stopping member both of which are located in the cavity. The distal end of the locking member is connected to the distal end of the occlusion body. The stopping member is disposed at the proximal end of the locking member. The proximal occluder head is provided with a locking hole in communication with the cavity. An occlusion device comprises the occluder, a hollow delivery' mechanism and a traction member. The distal end of the traction member is detachably connected to the proximal end of the locking member of the occluder after extending through the distal end of the delivery' mechanism. The occlusion device has a simple locking structure, and simplifies the manufacturing process and the locking operation.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.

Abstract: Techniques for encoding video with temporal layering are described, comprising predicting a sequence of pictures with a motion prediction reference pattern having a number of virtual temporal layers, and encoding the sequence of pictures into an encoded bitstream with a temporal layering syntax, wherein a number of signaled temporal layers is less than the number of virtual temporal layers. The number of signaled temporal layers may be determined from a target highest frame rate, a target base layer frame rate, and the number of virtual temporal layers.

Abstract: Techniques are disclosed for developing quantization matrices for use in video coding. According to these techniques a first quantization matrix may be derived from a second quantization matrix by scaling quantization values of the second quantization matrix by scaling parameters. The scaling parameters may increase according to distance between each matrix position and a matrix origin, they may be derived from characteristics of a video sequence to be coded, or both. The first quantization matrix may be communicated to a decoder. Thereafter, a video sequence may be coded predictively. As part of the coding, pixel data of the video sequence may be transformed to a plurality of frequency domain coefficients, and the frequency domain coefficients may be quantized according to the first quantization matrix.

Abstract: The present invention relates to an occluder (100), comprising a meshed occlusion body (I) provided with a cavity (103), and a proximal hub (2), as well as a locking member (10) and a stopping member (13) both of which are located in the cavity (103). The distal end of the locking member (10) is connected to the distal end of the occlusion body (1). The stopping member (13) is disposed at the proximal end of the locking member (10). The proximal occluder head (2) is provided with a locking hole (15) in communication with the cavity (103). The radial size of the stopping member (13) is slightly larger than the diameter of the locking hole (15). The radial size of the locking member (10) is smaller than the diameter of the locking hole (15), and at least one of the proximal occluder head (2) and the stopping member (13) is an elastic member. An occlusion device comprises the occluder (100), a hollow delivery mechanism (200) and a traction member (4).