Abstract: The present invention relates to a method, system, and storage medium for information search. The method for information search comprises: receiving an information search string inputted by a user; determining whether or not the information search string inputted by the user is complete, if the information search string inputted by the user is incomplete, then helping the user in completing the information search string; and, performing a search on the basis of the completed information search string. The method and system for information search of embodiments of the present invention combine user search history and user scenario to understand the intent of the user, to help the user in completing search information, to allow for searches of increased convenience and speed, and to increase the operability of the searches.

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

Abstract: A method and apparatus for automatically adding a tag to a document are provided. The method comprises: determining a plurality of candidate tag words corresponding to the document; determining a corpus comprising a plurality of texts; selecting commonly-used words from the corpus as characteristic words; determining, for each of the characteristic words and each of the candidate tag words, a probability for co-occurrence of the candidate tag word with the characteristic word; abstracting characteristic words from the document, and calculating a weight for each of the abstracted characteristic words; and calculating, in the corpus, a weighted probability for co-occurrence of each of the candidate tag words with all of the characteristic words abstracted from the document; selecting the candidate tag word with a high weighted co-occurrence probability as a tag word to be added to the document.

Abstract: A through silicon via (TSV), method and 3D integrated circuit are disclosed. The TSV extends through a substrate to a back side of the substrate and includes a body including a first metal for coupling to an interconnect on a front side of the substrate. A dielectric collar insulates the body from the substrate. The TSV also includes an end cap coupled to the body on the back side of the substrate, the end cap including a second metal that is different than the first metal. The end cap acts as a grinding stop indicator during back side grinding for 3D integration processing, preventing damage to the dielectric collar and first metal (e.g., copper) contamination of the substrate.

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract: Disclosed is a user interest recommending method and apparatus, where the method includes: obtaining, according to user-generated content of a social network, interest label information of users; clustering, according to the obtained interest label information, users having a same category of interest labels to form a cluster; and recommending interest labels of the users in the same cluster to the users in the cluster, and/or recommending the users in the same cluster to one another as friends with same interests. Because the interest labels of the users are obtained from user-generated content, accuracy of matching the interest labels is high. The interest labels or friends are recommended to the users in the cluster that is formed based on high accuracy, so the recommending accuracy is high, which improves recommending efficiency and the user interest labels.

Abstract: A method and apparatus for automatically adding a tag to a document are provided. The method comprises: determining a plurality of candidate tag words corresponding to the document; determining a corpus comprising a plurality of texts; selecting commonly-used words from the corpus as characteristic words; determining, for each of the characteristic words and each of the candidate tag words, a probability for co-occurrence of the candidate tag word with the characteristic word; abstracting characteristic words from the document, and calculating a weight for each of the abstracted characteristic words; and calculating, in the corpus, a weighted probability for co-occurrence of each of the candidate tag words with all of the characteristic words abstracted from the document; selecting the candidate tag word with a high weighted co-occurrence probability as a tag word to be added to the document.

Abstract: Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

Abstract: In some aspects of the present application, an apparatus for producing an interference pattern on a photosensitive portion formed on a surface of a sample is disclosed. The apparatus can include an optical system for providing interference between two coherent spherical wavefronts impinging on a thin-film photosensitive material formed on a surface of a sample, wherein a plane of the surface normal of the sample is arranged at an angle with respect to a plane defined by center propagation vectors of the two coherent spherical wavefronts; and one or more actuating elements operable to actuate one or more optical elements in the optical system, the sample, or both the one or more optical elements and the sample in one or more degrees of freedom to control a relative magnitude of a longitudinal and a transverse chirp of the interference pattern.

Abstract: Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.

Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

Abstract: Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

Abstract: Method, system, and computer readable medium for interest tag recommendation are provided in the present disclosure. Statistics about feature words of an Internet article related to an existing interest tag are collected to generate a characteristic vector of the existing interest tag. According to the characteristic vector of the existing interest tag, degree of similarity between the existing interest tag and an interest tag to be recommended is calculated. An interest tag is recommended according to the degree of similarity between the existing interest tag and the interest tag to be recommended.

Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

Abstract: A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Abstract: Various embodiments include interconnect structures and methods of forming such structures. The interconnect structures can include a composite copper wire which includes at least two distinct copper sections. The uppermost copper section can have a thickness of approximately 1 micrometer or less, which inhibits surface roughening in that uppermost section, and helps to enhance cap adhesion with overlying layers.